1. Introduction to Verilog (Behavioral Modeling)

2. Agenda Gate Delays and User-Defined Primitives Behavioral Modeling Design Examples Hands-on Practice

3. Gate Delays and User- Defined Primitives

4. Gate Delays Physical circuits exhibit propagation delay Therefore, necessary to specify delays in simulation Association of time unit with Physical time through compiler directive ‘timescale 1ns/100ps Compiler directive Unit of measurement Round-off unit What if no timescale is specified?

5. Gate-level model with propagation delays module cct_prop_delay(A,B,C,D,E) output D,E; input A,B,C; wire w1; and #(30) G1(w1,A,B); not #(10) G2 (E,C); or #(20) G3 (D,w1,E); endmodule

6. Output of Gates after Gate Delays Time units (ns) Inputs A B C Outputs E=C’ w1=A.B D=w1+E 10ns 30ns 20ns -000101 -111101 10111001 20111001 30111010 40111010 50111011

7. Output of Gates after Gate Delays

8. User-Defined Primitives UDP and system primitive UDP specification in terms of tabular form Rules for defining primitives 1. Keyword pair ---- primitive and endprimitive 2. One output listed first in the port list 3. The order of the inputs must conform with the one in the table that follows 4. Truth table keyword pair--- table and endtable 5. Values of inputs ending with colon following an output

9. Verilog model: (OR Gate) primitive UDP_123(C,A,B); output C; input A,B; table // A B : C 0 0 : 0; 0 1 : 1; 1 0 : 1; 1 1 : 1; endtable endprimitive

10. Verilog model:

12. LED Decoder Design LED DECODER switch1 switch2 switch3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg0 seg1seg2 seg6 seg4seg5 seg3 Seven Segment LED

13. 3-bit InputLED Display Seg[6543210] 000 1110111 001 0010010 010 1011101 011 1011011 100 0111010 101 1101011 110 1101111 111 1010010

14. Verilog module module test8bit(switch,seg); input [2:0]switch; output [7:0]seg; reg [7:0] seg; always @(switch) begin case(switch) 3'b000: seg=8'b01110111; 3'b001: seg=8'b00010010; 3'b010: seg=8'b01011101; 3'b011: seg=8'b01011011; 3'b100: seg=8'b00111010; 3'b101: seg=8'b01101011; 3'b110: seg=8'b01101111; 3'b111: seg=8'b01010010; endcase end endmodule

22. The Translate process converts the netlist output by the synthesizer into a Xilinx-specific format and adds with it the design constraints specified by user. The Map process decomposes the netlist and rearranges it so it fits nicely into the circuitry elements contained in the specified FPGA device. Then the Place & Route process assigns the mapped elements to specific locations in the FPGA and sets the switches to route the logic signals between them.

27. Pin Configuration for Nextek Training Board