1. All-Optical Header Processing in Optical Packet-Switched Networks Hoa Le Minh, Fary Z Ghassemlooy and Wai Pang Ng Optical Communications Research Group Northumbria Communications Research Lab Northumbria University U.K. July, 2005

2. Contents Overview of processing in optical networks Overview of processing in optical networks New Node Architecture New Node Architecture Proposed processing scheme Proposed processing scheme Results Results Summary Summary

3. Optical Communications  1 st generation optical networks: packet routing and switching are mainly carried out using high-speed electronic devices.  However, as the transmission rate continues to increase, electronically processing data potentially becomes a bottleneck at an intermediate node along the network.  Solution: All-Optical processing 1P 100T 10T 1T 100G 10G 1G 100M 1995 2000 2005 2010 [bit/s] Voice Data Total Traffic demand forecast (NEC–2001) Capacity increase : 2~4 times a year Bit cost decrease : 1/2 time a year

4. Future Optical Networks Source: NEC-2001

5. All-Optical Packet-Switched Networks (Core network) Edge Router Core Network Edge Router Edge Router Edge node O/E & E/O interface O/E & E/O interface Large routing table Large routing table Electronic processing Electronic processing Core node No O/E & E/O No O/E & E/O Wavelength labels Wavelength labels All-optical processing All-optical processing Edge Router Edge Router Edge Router Optical transparent ! PLH

6. All-Optical Packet-Switched Networks 2 2 9 9 45 13 5 5 10 AddressPortA_1P3 A_2P2 A_3P1 …… A_99P2 …… A_127P2 A_128P1 P1 P2 P3 23 8 8 6 6 All electronic node: O/E & E/O conversions  limit processing speed O/E & E/O conversions  limit processing speed All-Optical node: A large routing table – opt. memory issue Complexity O/EProcessingE/O Routing table for a network with 128 nodes A_99 H … 3 3 PLH

7. Electronic Processing Vs. Optical Processing AdvantagesDisadvantages ElectronicProcessing High processing  capacity  High processing  capacity  High scalability  High scalability  Low cost  Low cost  Large memory  Large memory  Able to support < 40Gbits/s Opticalprocessing Ultra-fast  Ultra-fast  (> 40Gbps) (> 40Gbps) Impractical complex configurations Impractical complex configurations Unavailable optical memory Unavailable optical memory Expensive Expensive

8. All-Optical Processing - Proposed Approach Offers Novel routing table in pulse-position modulation format Novel routing table in pulse-position modulation format –Small and fixed number of routing table entries regardless of the number of nodes in network. High scalability High scalability –Using simple optical configuration (SMZI). Ultrahigh speed and high capability Ultrahigh speed and high capability –Header address matching is done readily with reduced size routing table.

9. Proposed Header Processing Unit Matching pulse (Synchronized) Header Extraction PPM Conversion PPRT Delay fiber Data packet Pattern of port 1 Pattern of port 2 … Pattern of port M Optical AND gate 1 Optical AND gate 2 … Optical AND gate M All- Optical Switch All- Optical Switch … Control port 1Control port 2Control port M … Port 1 Port 2 Port M H Control Synchronization Clock Extraction HPLClk Optical Header Processor C[M]C[M] HPLClkHPLClk

10. Data Packet Format PayloadHeaderSync AddressOthers N bits (N optical pulses) Controls Parity … Data packet: -Optical pulses in RZ-format, - Speed a few hundreds Gbit/s - Each bit slot spreads from dozens to a few picoseconds 1 0 1 1 0 …

11. Pulse Position Modulation Format In PPM M-bit address symbol is converted into 2 M -slot symbol 1 0 0 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TbTb TsTs LSB T b – bit duration, T s – slot duration a 3 a 2 a 1 a 0 RZ Data PPM T sym 0 1 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T sym

12. PPM Generation Optical Circuit PP-format address: y(t) = x(t +  a i  2 i  T s ) N-bit address-codeword: A = [a i  {0,1}], i = 0, …, N SW1 SW2 SW3 SW4 20Ts20Ts 21Ts21Ts 22Ts22Ts 23Ts23Ts x(t)x(t)y(t)y(t) a0a0 a1a1 a2a2 a3a3 Header Ext. Unit Header Ext. Unit

13. PPM Based Routing Table AddressbitsDecimalweight Switch to port… 00…000 Port 2 00…011 Port 1 00…102 Port 3 00…113 Port 1 ……… 11…10 2 N -2 Port 2 11…11 2 N -1 Port 1 2 N entriesSwitchto Pulse- positions Actual PP frame (length 2 N slots) Port 1 (1,3,…,2 N -1) Port 2 (0,…,2 N -2) Port 3 (2,…) 0 1 2 3 4 2 N -1 … … … … … … 2 N - entry RT  M- entry PPM routing table M is fixed  number of entries is fixed at each node M = 3 i th Processing gain:

14. PPM Based Routing Table – contd. Is initialized with the clock synchronization. M entries are filled by: Is initialized with the clock synchronization. M entries are filled by: –Single optical pulse + Array of 2 N optical delay lines; Or, –M pattern generators + M optical modulators.

15. Ultrafast Optical AND Gate A/B01 000 101 Implementation: - Using optical interferometer configuration Terahertz Optical Asymmetric Demultiplexer (TOAD) SOA A B A.B B A SOA1 SOA2 Symmetric Mach-Zehnder Interferometer (SMZI)

16. All-Optical Switch 1 M1 M SMZI-1 SMZI-2 SMZI-M … C[1] C[2] C[M]C[M] 1 2 M Using an array of SMZI with controls provided from the processing unit

17. Simulation Parameters ParametersValue Data bitrate50Gbits/s Data packet length53 bytes (424 bits) Data packet guard time3 ns Header length4 bits Data power (per pulse)2mW Data pulse width (FWHM)1 ps PPM slot T s 5 ps Wavelength1554 nm

18. Simulation Results Extracted clocks Incoming packet

19. Switched Outputs Node 1 Node 2 Node 3

20. Summary A novel node architecture encooprating all optical processing with much reduced routing table entries based om PPM was proposed and simulated using VPI simulation package. A novel node architecture encooprating all optical processing with much reduced routing table entries based om PPM was proposed and simulated using VPI simulation package. It is possible to significantly increase the number of nodes in network as well as enlarge the size or routing table at each node without introducing large processing delay. It is possible to significantly increase the number of nodes in network as well as enlarge the size or routing table at each node without introducing large processing delay.

21. Acknowledgements One of the authors Hoa Le Minh is sponsored by the Northumbria University for his PhD study. One of the authors Hoa Le Minh is sponsored by the Northumbria University for his PhD study.

22. Thank you!