1. 9/08/05ELEC5970-001/6970-001 Lecture 51 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Dual-Threshold Low-Power Devices Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu

2. 9/08/05ELEC5970-001/6970-001 Lecture 52 Subthreshold Conduction V gs – V t -V ds I ds =I 0 exp( ───── ) × (1– exp ── ) nv th v th Sunthreshold slope 0 0.3 0.6 0.9 1.2 1.5 1.8 V V gs I ds 1mA 100μA 10μA 1μA 100nA 10nA 1nA 100pA 10pA VtVt Subthreshold region Saturation region

3. 9/08/05ELEC5970-001/6970-001 Lecture 53 Thermal Voltage, v th v th = kT/q = 26 mV, at room temperature. When V ds is several times greater than v th V gs – V t I ds =I 0 exp( ───── ) nv th

4. 9/08/05ELEC5970-001/6970-001 Lecture 54 Leakage Current Leakage current equals I ds when V gs = 0 Leakage current, I ds = I 0 exp(-V t /nv th ) At cutoff, V gs = V t, and I ds = I 0 Lowering leakage to 10 -k I 0 V t = knv th ln 10 = 1.5× 26 ln 10 = 90k mV Example: To lower leakage to I 0 /1,000 V t = 270 mV

5. 9/08/05ELEC5970-001/6970-001 Lecture 55 Threshold Voltage V t = V t0 + γ[(Φ s +V sb ) ½ - Φ s ½ ] V t0 is threshold voltage when source is at body potential (0.4 V for 180nm process) Φ s = 2v th ln(N A /n i ) is surface potential γ = (2qε si N A ) ½ t ox /ε ox is body effect coefficient (0.4 to 1.0) N A is doping level = 8×10 17 cm -3 n i = 1.45×10 10 cm -3

6. 9/08/05ELEC5970-001/6970-001 Lecture 56 Threshold Voltage, V sb =1.1V Thermal voltage, v th = kT/q = 26 mV Φ s = 0.93 V ε ox = 3.9×8.85×10 -14 F/cm ε si = 11.7×8.85×10 -14 F/cm t ox = 40 A o γ = 0.6 V ½ V t = V t0 + γ[(Φ s +V sb ) ½ - Φ s ½ ] = 0.68 V

7. 9/08/05ELEC5970-001/6970-001 Lecture 57 A Sample Calculation V DD = 1.2V, 100nm CMOS process Transistor width, W = 0.5μm OFF device (V gs = V t ) leakage I 0 = 20nA/μm, for low threshold transistor I 0 = 3nA/μm, for high threshold transistor 100M transistor chip Power = (100×10 6 /2)(0.5×20×10 -9 A)(1.2V) = 600 mW, for all low-threshold transistors Power = (100×10 6 /2)(0.5×3×10 -9 A)(1.2V) = 90 mW, for all high-threshold transistors

8. 9/08/05ELEC5970-001/6970-001 Lecture 58 Dual-Threshold Chip Low-threshold only for 20% transistors on critical path. Leakage power = 600×0.2 + 90×0.8 = 120 + 72 = 192 mW

9. 9/08/05ELEC5970-001/6970-001 Lecture 59 Dual-Threshold CMOS Circuit

10. 9/08/05ELEC5970-001/6970-001 Lecture 510 Dual-Threshold Design To maintain performance, all gates on the critical path are assigned low V t. Most of the other gates are assigned high V t. But, Some gates on non-critical paths may also be assigned low V t to prevent those paths from becoming critical.

11. 9/08/05ELEC5970-001/6970-001 Lecture 511 Integer Linear Programming (ILP) to Minimize Leakage Power Use dual-threshold CMOS process First, assign all gates low V t Use an ILP model to find the delay (Tc) of the critical path Use another ILP model to find the optimal V t assignment as well as the reduced leakage power for all gates without increasing Tc Further reduction of leakage power possible by letting Tc increase

12. 9/08/05ELEC5970-001/6970-001 Lecture 512 ILP -Variables For each gate i define two variables. Ti: the longest time at which the output of gate i can produce an event after the occurrence of an input event at a primary input of the circuit. Xi: a variable specifying low or high V t for gate i; Xi is an integer [0, 1]. 1  gate i is assigned low V t ; 0  gate i is assigned high V t.

13. 9/08/05ELEC5970-001/6970-001 Lecture 513 ILP - objective function - minimize the sum of all gates leakage currents, given by I Li is the leakage current of gate i with low V t ; I Hi is the leakage current of gate i with high V t ; Using SPICE simulation results, construct a leakage current look up table, which is indexed by the gate type and the input vector. Leakage power:

14. 9/08/05ELEC5970-001/6970-001 Lecture 514 ILP - Constraints For each gate (1) gate j ‘s output is gate i ‘s fan in (2) Max delay constraints for primary outputs (PO) (3) T max is the maximum delay of the critical path

15. 9/08/05ELEC5970-001/6970-001 Lecture 515 ILP Constraint Example assume all primary input (PI) signals on the left arrive at the same time. For gate 2, constraints can be given by

16. 9/08/05ELEC5970-001/6970-001 Lecture 516 ILP – Constraints (cont.) D Hi is the delay of gate i with high V t D Li is the delay of gate i with low V t A second look-up table is constructed and specifies the delay for given gate type and fanout number.

17. 9/08/05ELEC5970-001/6970-001 Lecture 517 ILP – Finding Critical Delay T max can be specified or be the delay of longest path (Tc). To find Tc, we change constraints (2) to an equation, assigning all gates with low V t. Maximum Ti in the ILP solution is Tc. If we replace T max with Tc, the objection function minimizes leakage power without sacrificing performance.

18. 9/08/05ELEC5970-001/6970-001 Lecture 518 Power-Delay Tradeoff If we gradually increase Tmax from Tc, leakage power is further reduced, because more gates can be assigned high V t. But, the reduction trends to become slower. When Tmax = (130%) Tc, the reduction is about saturated, because almost all gates are assigned high V t. Maximum leakage reduction can be 98%.

19. 9/08/05ELEC5970-001/6970-001 Lecture 519 Power-Delay Tradeoff

20. 9/08/05ELEC5970-001/6970-001 Lecture 520 Leakage Reduction Cir. Number of gates T c (ns) Unoptim ized I leak (μA) Optimiz ed I leak (μA) (T max =T c ) Leakage Reducti- on % Sun OS 5.7 CPU secs. Optimized I leak (μA) (T max =1.25T c ) Leakage Reducti- on % Sun OS 5.7 CPU secs. C4321600.752.6201.02261.00.250.13295.00.25 C4991820.394.2933.46419.30.310.22594.80.30 C8803280.674.4060.52488.10.540.15396.50.53 C13552140.404.3883.29025.00.330.29493.30.36 C19083190.576.0232.02366.40.570.20496.60.56 C26703621.265.9250.65990.40.680.12597.90.53 C354010971.7515.6220.97293.81.710.31998.01.70 C531511651.5919.3322.50587.11.820.39598.01.83 C628811772.1823.1426.07573.82.070.67897.12.00 C755210461.9222.0430.87296.01.590.44598.01.68

21. 9/08/05ELEC5970-001/6970-001 Lecture 521 Dynamic & Leakage Comparison v th (thermal voltage, kT/q) and V t both depend on the temperature; leakage current also strongly depends on temperature. Spice simulation shows that for a 2-input NAND gate - with low V t, I sub @ 90ºC = 10 × I sub @ 27ºC - with high V t, I sub @ 90ºC = 20 × I sub @ 27ºC To manifest the projected contribution of leakage to the total power, we compare dynamic and leakage power @ 90ºC.

22. 9/08/05ELEC5970-001/6970-001 Lecture 522 Results-Dynamic & Leakage Comparison (cont.) Without considering glitches, the dynamic power is estimated by an event driven simulator, and is given by We apply 1000 random test vectors at PIs with a vector period of 120% Tc, and calculate the total number of weighted (by node capacitance) transitions in the circuit.

23. 9/08/05ELEC5970-001/6970-001 Lecture 523 Dynamic & Leakage Power (cont.) Circuit P dyn (μW) P leak1 (μW) P leak1 / P dyn % P leak2 (μW) P leak2 / P dyn % C43271.1726.2036.810.2214.3 C499149.8142.9328.734.6423.1 C880135.1944.0632.65.243.8 C1355162.3943.8827.032.9020.3 C1908185.6060.2333.420.2310.9 C267092.6459.2564.06.597.1 C3540218.41156.2271.59.724.4 C5315299.61193.3264.625.058.4 C6288215.12231.42108.060.7528.2 C7552229.13220.4396.28.723.8

24. 9/08/05ELEC5970-001/6970-001 Lecture 524 Dynamic & Leakage Power (cont.)

25. 9/08/05ELEC5970-001/6970-001 Lecture 525 Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for V t Assignment and Path Balancing Yuanlin Lu VLSI Design and Test Seminar Broun 235 September 14, 2005, 3:00PM