1. 1 Farhan Mohamed Ali (W2-1) Jigar Vora (W2-2) Sonali Kapoor (W2-3) Avni Jhunjhunwala (W2-4) Presentation 7 MAD MAC 525 8 th March, 2006 Functional Block Layout and Floorplan W2 Project Objective: Design a crucial part of a GPU called the Multiply Accumulate Unit (MAC) which will revolutionize graphics. Design Manager: Zack Menegakis

2. 2 MAD MAC 525 Status: Project chosen Specifications defined Architecture Design Behavioral Verilog Testbenches Verilog : Gate Level Design Floor plan Schematics and Analog Verifications Layout of basic gates and small blocks  To be done  Layout of large scale blocks (in progress)  Extraction, LVS, post-layout simulation

3. 3 Block Diagram RegArray ARegArray BRegArray C Multiplier Exp CalcAlign Adder/Subtractor Control Logic & Sign Dtrmin Normalize Round Ovf Checker Leading 0 Anticipator 10 5 5 5 14 35 22 5 4 36 14 10 1 5 5 Input Output 16 Reg Y 15 1 1 1

4. 4 Design Decisions Pipelining Stages: Based on delays decided on where we are going to pipeline. Could possibly add another stage in multiplier as adder is fast. New adder design which implements carry look ahead architecture and has propagation delay at 1.34ns

5. 5 Pipeline Reg Pipelining Stages Multiplier Align C Reg A Reg B Exp Calc Reg C Pipeline Reg Adder Ld Zero Pipeline Reg Normalize Round Reg Y Pipeline Reg Overflow checker

6. 6 Timing Diagram Pipeline stage 1 Pipeline stage 2 Pipeline stage 3 Pipeline stage 4 Multiplier lower 9 outputs Multiplier top 13 outputs AdderNormalize Exponent calculator AlignZero Counter Round Holds exponent calculator bits Overflow Checker

7. 7 Adder Schematic

8. 8 Adder Schematic Simulation

9. 9 Transistor Count Area in um 2 Prop. Delay Power in mW (350MHz) Multiplier3600165604.64n8.5 Exponents824 4200942p1.608 Align396 1980480p1.031 Adder3116155801.34n4.58 Leading 0364 1222551p0.857 Normalize942 4710430p2.291 Round252 12601.42n0.198 OvfCheck98 500743p0.13 Registers1850 9200120p- Total 1144255212--

10. 10 Multiplier Layout

11. 11 Multiplier Simulation

12. 12 Multiplier Simulation

13. 13 Shifter Layout

14. 14 Shifter Bit

15. 15 Zerocounter Layout

16. 16 ZeroCounter Simulation

17. 17 Problems Pathmill vs Us: Tried to verify critical path with Pathmill - gives bigger delays for some modules than analog simulation - critical path does not appear to be correct

18. 18 Questions??