1. 2-1 ECE 424 Design of Microprocessor-Based Systems Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901 Fundamentals of Digital Logic and Binary Number Representation

2. 2-2 Digital Signals and Basic Logic Gates  Digital signal values True1High Voltage (e.g. 5V) 12 False0Low Voltage (e.g. 0V)  Basic logic gates 1. Inverter Truth Table of an inverter X Y = X XY 1001XY 1001 2. AND X Y Z = X  Y XYZ 000010100111XYZ 000010100111 Truth Table of an AND gate 3. NAND X Y Z = X  Y

3. 2-3 Basic Logic Gates 4. OR XYZ 000011101111XYZ 000011101111 X Y Z = X + Y Truth Table of an OR gate 5. NOR X Y Z = X + Y 4. XOR XYZ 000011101110XYZ 000011101110 Truth Table of an XOR gate 5. XNOR X Y Z = X  Y +X  Y X Y Z = X + Y

4. 2-4 Basic Logic Gates  Tri-state Buffer I O C CI O 1X Z 00 0 01 1 Truth table of a tri-state buffer I1 I2 S O 2-to-1 multiplexer C Y Bi-direction circuit X Mux

5. 2-5 Decoder Circuits  2-to-4 decoder implementation X Y Z1 (00) Z2 (01) Z3 (10) Z4 (11) X Y Z1 Z2 Z3 Z4 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1  A decoder circuit uniquely selects one of its outputs according to its input signals Decoder  N inputs 2 N outputs

6. 2-6 Decoder Circuit  3-to-8 decoder implementation  Assume that we have 2-to-4 decoders available as standard components CS X Y  When CS is low (0), all the outputs of the decoder are low (0) CS X Y X Y X Y Z 2-to-4 decoder

7. 2-7 Sequential Logic Circuits  D latch  D Flip-flop CLK DQ Q D Q  When CLK=1, Q always reflects the signal value at input D  If CLK=0, Q stores the last D value which appears at D just before CLK falls to 0  When a negative edge appears at CLK input, D Flip-flop updates Q to the current D value  D flip-flop will not change its output values unless there is a negative edge event at CLK input (CLK switches from logic 1 to 0). CLK DQ Q D Q

8. 2-8 Sequential Logic Circuits  Counter  Basic binary counter  Synchronous counter D Q Q DFF D Q Q D Q Q CLK ABC ClkC B A Init. 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 D Q Q DFF D Q Q D Q Q CLK A B C

9. 2-9  frequency divider Sequential Logic Circuits  Divide clock frequency by 4  Divide clock frequency by 3 D Q Q DFF D Q Q CLK CLK_4 CLK CLK_4 CLK D Q Q DFF D Q Q CLK_3 CLK CLK_3

10. 2-10  Register Sequential Logic Circuits  A row of storage elements (e.g. D flip-flops)  Shift register D Q Q DFF D Q Q CLK D Q Q DFF D Q Q Data Q3Q2Q1Q0 Q[3:0] D Q Q DFF D Q Q CLK D Q Q DFF D Q Q Q3Q2Q1Q0 0 CLKQ3 Q2 Q1 Q0 Init.1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0

11. 2-11 Memories Circuits Column decoder  Row decoder  N/2 bit address N/2 bit address Memory location  Memories are storage devices containing a large number of storage locations  Addressing space: total number of memory locations  If a memory device has N bit addresses, it has 2 N memory locations

12. 2-12 Memory Types  ROM v.s. RAM  ROM: Read-Only Memory  RAM: Random Access Memory (allow both read and write operations)  Volatile v.s. Non-volatile  Volatile: memory loses data after power is off  Non-volatile: memory keep stored data even after power is off Mask ROM PROMEPROMEEPROMFlash memory MRAMSRAMDRAM Non-volatileVolatile

13. 2-13 Memory Addressing  Example  Use memory chips with the capacity of 1K (1024 bit) to construct a 2K memory system 1K CS 1K CSW/R Addr[10] Addr[9:0]

14. 2-14 Binary Number System  Converting binary numbers to decimal numbers 1011  1*2^3 + 0*2^2 + 1*2^1 + 1*2^0 = 11 0111  0*2^3 + 1*2^2 + 1*2^1 + 1*2^0 = 7 BinaryDecimal  Converting binary numbers to hexadecimal numbers 1 1 1 1 0 1 0 1 1 0 1 0 0 0 1 1 3A 5 F

15. 2-15 Binary Addition 0 1 1 0 0 1+ 1 1 1 0  Example  A single-bit full adder  4-bit adder Full adder Full adder Full adder Full adder A[0]B[0]A[1]B[1]A[2]B[2]A[3]B[3] S[0]S[1] S[2] S[3] C_in C_out C_0C_1C_2 Full adder S C_in C_out AB

16. 2-16 Handling Negative numbers  One’s complement  For p ositive number A, it is represented as usual binary number  For negative number -A, its representation is obtained by flipping the bits of the binary representation of A 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 1 1 0 1 1 0 -1 1 0 1 -2 1 0 0 -3 1’s complementDecimal  Signed magnitude  The left-most bit is a sign bit 0 indicates positive a number and 1 indicates negative a number 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 0 1 0 1 -1 1 1 0 -2 1 1 1 -3 Signed magnitudeDecimal

17. 2-17 Handling Negative numbers  Two’s complement 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 1 1 -1 1 1 0 -2 1 0 1 -3 1 0 0 -4 2’s complementDecimal  For p ositive number A, it is the same as the one’s complement  For negative number A, add one to the one’s complement representation 3  1 2 0 1 1 + 1 1 1 1 0 1 0 Overflow Ignore 2 2  3 0 1 0 + 1 0 1 1 1 1  By using two’s complement number representation, minus operations can be performed by adders