1. Noise Canceling in 1-D Data: Presentation #13 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 April 20 th, 2005 Short Final Presentation Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware Project Manager: Bobby Colyer

2. Status Design proposal (Done) Architecture proposal (Done) Size Estimates and Floorplan (Done) Gate Level Design - Schematics (Done) –Layout (Done) To be done: –Spice simulation (In Progress)

3. FPAdder Updates −Both simulations work −No more weird funky outputs

4. FPAdder1: ExtractedRC Simulations Results

5. FPAdder2: ExtractedRC Simulations Results

6. Final Presentation Outline

7. Noise Canceling in 1-D Data Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 Project Manager: Bobby Colyer

8. Project Description −What does the chip do? −It is part of the a research done by a CMU Robotics faculty −How does it fit in the big picture −Why did we find this interesting

9. Marketing Potential −Medical/ robotic applications −Rehabilitation/ human-computer interfaces −Vehicle maneuvering −Hearing aid −Computer devices applications −** can be implemented in other applications

10. Behavioral/ Algorithmic Description −How the top level works −Communications between toplevel modules −Datapath (Block Diagram) −Input/Output

11. Design Process −Research done in CMU (want to implement the software into hardware −Main target : to have optimum power saving feature −Design tradeoffs between different implementation of major blocks −Decision based on design goals (worked in parallel) −C code / Behavioral Verilog / Structrural Verilog −Schematics / Layout

12. Floorplan Evolution −All the steps that we went through

13. Verification Process −Codes −Schematics −Layout −Timing

14. Issues Encountered −Floating point numbers (too small) −Issues for major modules −Adders −Multipliers −DFFs −Timing issues −Signal strength −Ways to solve the problems

15. Chip Specification − Physical properties –Size/ Dimension –Transistor count –Area/ density –Pin-outs –Throughput –Frequency − Pin specs –Inputs/outputs/constants –Descriptions − Part specs –Major blocks properties

16. Layout −Layout masks –Poly –Metal 1 –Metal 2 –Metal 3 –Metal 4 −Full chip layout −Final floorplan with final chip

17. Conclusion −Summary of projects −Improvements in future −Importance of optimization/ good floor planning/ team communication