1. Insertion Sort using FPGA’s Aaron Tiedje CSE 670 Winter 2004 March 1, 2004 Professor R. Haskell Embedded Systems using FPGA's

2. Input MUX Input Register Switches Clock Input Load Temp Clear Memory Block Clock Memory Clear Mem Load < Switch Flag Temporary Register Temp Load Clock Waste ClearWaste Counter Waste Inc Clock Total ClearTotal Counter Total Inc Clock Index ClearIndex Counter Index Inc < Next Location < Sort Done Size < Display Done Sort Data Path

3. Sort Control Path s0 Reset and clear everything s1 Read first input s2 When button released: Insert into first memory location Increment total input counter s3 Read next input Increment total input counter s4 Waiting for button release s5 Is current input < current memory location? Yes Save current memory value into temporary register s41 Extra state S42 Copy temp register value into input register s40 Store input into current memory location

4. Sort Control Path cont. Yes - s7 Save current input value to memory Yes - s9 Clear the memory address for displaying the first number s6 At the end of the entered list yet? No - Go back to s4 s8 All 10 values entered yet? No - Go back to s3 s10 Clear the time waste counter s11 Waste one clock cycle while displaying number s12 Have we wasted enough time yet? Yes - s13 Have we displayed all the numbers yet? Yes – Reset memory index No – Increment memory address index

5. Instructions & Notes BN resets the state machine BTN4 latches an input Enter 10 numbers via the DIP switches in random order During data entry, the display will show the largest value already entered Pressing BTN3 will display the number of inputs (minus 1) entered thus far After data entry, the display will cycle the 10 inputs in numerical order