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Communication IC & Signal Processing Lab. Chih-Peng Fan1 PostSim CoreGenerator IP in ISE 5.1i with Verilog HDL.

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Presentation on theme: "Communication IC & Signal Processing Lab. Chih-Peng Fan1 PostSim CoreGenerator IP in ISE 5.1i with Verilog HDL."— Presentation transcript:

1 Communication IC & Signal Processing Lab. Chih-Peng Fan1 PostSim CoreGenerator IP in ISE 5.1i with Verilog HDL

2 Communication IC & Signal Processing Lab. Chih-Peng Fan2 Step 1. Compile postsim libarary compxlib -s mti_pe -f all -l all -o c:\modeltech_5.6b\xilinx_libs

3 Chih-Peng Fan3 Step 2. Create postsim libarary Verilog lib

4 Communication IC & Signal Processing Lab. Chih-Peng Fan4 Step 3. Run Xilinx CORE Generator

5 Communication IC & Signal Processing Lab. Chih-Peng Fan5 Step 4. Choose Multiplier IP

6 Communication IC & Signal Processing Lab. Chih-Peng Fan6 Step 5. Create files from CORE Generator

7 Communication IC & Signal Processing Lab. Chih-Peng Fan7 Step 6. Prepare a top file for mult8x8.v (from CoreGen) module Top_mult8x8(a,b,o); input [7:0] a,b; output [15:0] o; // ----- Begin Cut here for INSTANTIATION Template --- // INST_TAG mult8x8 ttt (.a(a),.b(b),.o(o)); // INST_TAG_END endmodule Top_mult8x8.v

8 Communication IC & Signal Processing Lab. Chih-Peng Fan8 Step 7. Run Synplify_Pro Synthesizer

9 Communication IC & Signal Processing Lab. Chih-Peng Fan9 Step 8. Add two files in the project

10 Communication IC & Signal Processing Lab. Chih-Peng Fan10 Step 9. Prepare two files for implement Generate from CoreGenGenerate from Synplify_Pro

11 Communication IC & Signal Processing Lab. Chih-Peng Fan11 Step 10. Run Xilinx ISE 5.1i with EDIF design flow

12 Communication IC & Signal Processing Lab. Chih-Peng Fan12 Step 11. Add *.edn and *.edf in the project

13 Communication IC & Signal Processing Lab. Chih-Peng Fan13 Step 12. Set the postsim generated files

14 Communication IC & Signal Processing Lab. Chih-Peng Fan14 Step 13. Generate postsim *.v and *.sdf

15 Communication IC & Signal Processing Lab. Chih-Peng Fan15 Step 14. Prepare files for post-simulation

16 Communication IC & Signal Processing Lab. Chih-Peng Fan16 Step 15. Run ModelSim, then change the directory

17 Communication IC & Signal Processing Lab. Chih-Peng Fan17 Step 16. Create a New library

18 Communication IC & Signal Processing Lab. Chih-Peng Fan18 Step 17. Run *.do batch file in command window

19 Communication IC & Signal Processing Lab. Chih-Peng Fan19 Step 18. Create a waveform window Mouse right click

20 Communication IC & Signal Processing Lab. Chih-Peng Fan20 Step 19. Run, then produce the waveform

21 Communication IC & Signal Processing Lab. Chih-Peng Fan21 Appendix glbl.v test_mult8x8.v timesim.v fpga1.f vlog -f fpga1.f vsim -L C:/Modeltech_5.7c/examples/Xilinx_libs/simprim_ver -L C:/Modeltech_5.7c/examples/Xilinx_libs/unisim_ver -L C:/Modeltech_5.7c/examples/Xilinx_libs/XilinxCoreLib_ver -sdftyp /mult2=c:/test-postsim/PS/timesim.sdf work.stimulus work.glbl fpga1.do You must modify the lib path You must modify the applied region name

22 Communication IC & Signal Processing Lab. Chih-Peng Fan22 test_mult8x8.v `timescale 1ns / 100ps module stimulus; reg[7:0] A,B; wire[15:0] PRODUCT; reg CLK; reg Reset; reg [15:0] D_PRODUCT; reg [7:0] IN_A [3:0]; reg [7:0] IN_B [3:0]; reg [1:0] index; // -------------------------------- Top_mult8x8 mult2 (A,B,PRODUCT); // ------------------------------- always #10 CLK=~CLK; initial begin Reset=1'b0; CLK=1'b0; #25 Reset=1'b1; end ………… ………….

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