1. Practically Realizing Random Access Scan By Anand Mudlapur ECE Dept. Auburn University

2. 03/10/200415th GSC Forum2 Serial Scan FF Combinational Circuit PIPO Scan-in Scan-out Consider a circuit with 5,000 FFs and 10,000 test vectors Total test cycles = 5,000 x 10,000 + 10,000 + 5,000 = 50,015,000 !!! 1. Every digital system fits into this model 2. Limited by Controllability of the states During every test, only a subset of all the Flip-flops need to be set and observed for targeted faults

3. 03/10/200415th GSC Forum3 Random Access Scan (RAS) Concurrent solution to most of the problems in SS testing Each scan-cell is randomly and uniquely addressable Reduces both test application time as well as test power consumption, simultaneously, which are otherwise complementary objectives FF Combinational Circuit PIPO Decoder Address inputs Scan-out

4. 03/10/200415th GSC Forum4 RAS Architecture [SALUJA et al 04]

5. 03/10/200415th GSC Forum5 Our RAS Architecture RAS-FF RAS signals RAS-FF AddressedUnaddressed Hold states Toggle previous state

6. 03/10/200415th GSC Forum6 Routing Flip-flops

7. 03/10/200415th GSC Forum7 Area overhead n ff = number of FFs n g = number of gates A circuit with 5120 gates and 512 FFs Gate overhead of serial scan = 20 % Gate overhead of RAS = 30.2 % Gate overhead of scan = 4 x n ff n g + 10 x n ff X 100 % Gate overhead of RAS = 6 x n ff + √n ff n g + 10 x n ff X 100 % A circuit with 20480 gates and 512 FFs Gate overhead of serial scan = 8 % Gate overhead of RAS = 12 %

8. 03/10/200415th GSC Forum8 Delay testing using RAS Normal scan sequential circuits can be tested for delay faults, but the vector- pairs must be specially generated A one bit change is desired while targeting a delay fault In RAS vector V1 is setup and vector V2 can be subsequently applied without any constraints

9. 03/10/200415th GSC Forum9 Results The architecture was implemented on ISCAS benchmark circuits and the fault coverage were the same as that of serial scan A reduction of up to 60% can be observed just by modifying the existing ATPGs Relative reduction of power dissipation in the circuit is calculated assuming that, the power dissipated is directly proportional to the number of transitions in the primary inputs and states of FFs. [Devadas et al. 95] It can be observed that, as the size of the circuits increases, reduction in power dissipation upto 99% is achieved using RAS.

10. 03/10/200415th GSC Forum10 Results

11. 03/10/200415th GSC Forum11 Modification of PODEM’s Backtrace algorithm RAS-FF Cost function associated with controllability is set very high A B C D

12. 03/10/200415th GSC Forum12 Conclusion Skepticism towards RAS in the past has mainly been due to the excessive area overhead in the form of routing and suggested architectures RAS is an ideal solution to target test volume and test power which are otherwise complementary Efficiently laying out the circuit and deploying the decoders optimally would keep the area overhead to a minimum