1. Lecture 14: Review Intro to IT COSC1078 Introduction to Information Technology Lecture 14 Revision and Review James Harland james.harland@rmit.edu.au

2. Lecture 14: ReviewIntro to IT Introduction to IT 1-4 Introduction, Images, Audio, Video 5-6 Computer Fundamentals Assignment 1, WebLearn Test 1 7 Review 8 Operating Systems WebLearn Test 2 9 Operating Systems Assignment 2 10 Internet 11 Internet Security WebLearn Test 3 12 Future of ITAssignment 3, Peer and Self Assessment

3. Lecture 14: ReviewIntro to IT Overview  Questions?  Floating point numbers  “Week 6 lectures”  Questions?

4. Lecture 14: ReviewIntro to IT Excess Notation Bit patternValue 1113 1102 1011 1000 011 010-2 001-3 000-4 A different encoding of the numbers “naive” bit pattern encodes 4 more than actual value 100 (looks like 4) encodes 0 101 (looks like 5) encodes 1 110 (looks like 6) encodes 2 ….

5. Lecture 14: ReviewIntro to IT Floating Point sign bit Mantissa exponent 1 bit for sign 3 bits for exponent 4 bits for mantissa 100.101

6. Lecture 14: ReviewIntro to IT Floating Point 01011001 means +ve 0.1001 shifted 101 place = 1.001  Mantissa: digit sequence (1 st digit always 1)  Exponent: where to put the.  This is generally given in ‘excess’ notation  Binary form of 2.423 x 10 4

7. Lecture 14: ReviewIntro to IT Memory  Memory differs in performance and cost  Processor is typically much faster than memory

8. Lecture 14: ReviewIntro to IT Memory  Arranged as a hierarchy of cache Level 1 Level 2 Level 3 Main Memory

9. Lecture 14: ReviewIntro to IT Processing ALU CPU BUS REGISTERS MEMORY

10. Lecture 14: ReviewIntro to IT Machine Instructions 1.Move first value from memory into register 1 2.Move second value from memory into register 2 3.If register 2 is zero, go to Step 6 4.Divide register 1 by register 2 & store result in register 3 5.Store register 3 value in memory 6.Stop “Divide two numbers”

11. Lecture 14: ReviewIntro to IT Instructions in Binary? 01010100001010101010100110100010101001101001010010 100011100010101010100101111001001010… LOAD register 1 LOAD register 2 JUMP …. STORE …. 10101100 10110011 00010010 00110011 00111111 MEMORY

12. Lecture 14: ReviewIntro to IT One Scheme 16-bit operation codes (simple example) Operation Code (4 bits) Operand (12 bits) Represent as 4 Hexadecimal numbers (0-9,A-F) Each instruction is two bytes long

13. Lecture 14: ReviewIntro to IT One Scheme 156C LOAD register 5 from memory 6C 166D LOAD register 6 from memory 6D 5056 ADD register 5 & 6 & store in register 0 306E STORE register 0 to memory 6E C000 HALT.... (up to 2 16 = 65,536 different instructions)

14. Lecture 14: ReviewIntro to IT Fetch Decode Execute FETCH EXECUTEDECODE Machine cycle

15. Lecture 14: ReviewIntro to IT Two special registers Instruction register: holds current instruction Program counter: address of next instruction Fetch: Put instruction specified by program counter into instruction register Increment program counter by two Decode: Work out what to do Execute: Perform the instruction

16. Lecture 14: ReviewIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A0 AddressContents

17. Lecture 14: ReviewIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A0 FETCH 156C

18. Lecture 14: ReviewIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A2 FETCH 156C

19. Lecture 14: ReviewIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A2 DECODE 156C 6C 2B

20. Lecture 14: ReviewIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A2 EXEC 156C 6C 2B 2B5

21. Lecture 14: ReviewIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A2 FETCH 166D

22. Lecture 14: ReviewIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A4 FETCH 166D

23. Lecture 14: ReviewIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A4 DECODE 166D

24. Lecture 14: ReviewIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A4 EXEC 166D 6D FF FF6

25. Lecture 14: ReviewIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register A6 FETCH 5056

26. Lecture 14: ReviewIntro to IT Processing A0 15 A1 6C A2 16 A3 6D A4 50 A5 56 A6 30 A7 C0 A8 C0 A9 00 Program Counter Instruction Register …

27. Lecture 14: ReviewIntro to IT Processing Program Counter Instruction Register EXEC B258 B4

28. Lecture 14: ReviewIntro to IT Processing Program Counter Instruction Register EXEC B258 58

29. Lecture 14: ReviewIntro to IT Connecting devices ??

30. Lecture 14: ReviewIntro to IT Universal Serial Bus (USB)

31. Lecture 14: ReviewIntro to IT Memory-mapped I/O Program Counter Instruction Register C4 EXEC 3634 34 FF FF6 Just like writing to a memory address

32. Lecture 14: ReviewIntro to IT Direct Memory Access (DMA) Put some data in memory! OK

33. Lecture 14: ReviewIntro to IT Direct Memory Access Direct Memory Access means that doesn’t have to wait for the

34. Lecture 14: ReviewIntro to IT Busy Bertie the bus … Von Neumann bottleneck

35. Lecture 14: ReviewIntro to IT Conclusion  Assignment 2 specified sometime this week  Finish reading book!