1. Flip-Flops Module M10.2 Section 7.1

2. D Latch Q !Q CLK D !S !R S R 0 1 1 1 1 0 X 0 Q 0 !Q 0 D CLK Q !Q Note that Q follows D when the clock in high, and is latched when the clock goes to zero.

3. D Flip-Flop 0 1 1 1 1 0 X 0 Q 0 !Q 0 D NCK Q !Q Q !Q D !S !R S R CLK Pulse-narrowing circuit NCK 0 0 1 1 1 0 X 0 Q 0 !Q 0 D CLK Q !Q

4. Pulse-Narrowing Circuit

5. D Flip-Flop CLK DQ !Q 0 0 1 1 1 0 X 0 Q 0 !Q 0 D CLK Q !Q D gets latched to Q on the rising edge of the clock. Positive edge triggered

6. D Flip-Flop CLK DQ !Q y CLK z pulse width setup time hold time propagation delay

7. Making a positive edge-triggered D Flip-Flop from Master-Slave D Latches CLK xzy D E QD E Q CLK’ inputoutput x y z CLK’ CLK masterslave

8. D Flip-Flop CLK DQ !Q 0 0 1 1 1 0 X 0 Q 0 !Q 0 D CLK Q !Q D gets latched to Q on the rising edge of the clock. Positive edge triggered

9. GAL 16V8 D Flip-Flops

10. Divide-by-2 Counter CLK Q0 Q0.D = !Q0 CLK DQ !Q Q0.D = !Q0 Q0 Q0.D !Q0

11. div2cnt.abl MODULE Div2Cnt TITLE 'Divide By 2 Counter, A. Student, 7/20/02' DECLARATIONS " INPUT PINS " PB PIN 10; " push-button switch (clock) " OUTPUT PINS " Q0 PIN 35 ISTYPE 'reg buffer'; " LED 8 [A,B,C,D,E,F,G,DP] PIN 15,18,23,21,19,14,17,24 ISTYPE 'com'; Segments = [A,B,C,D,E,F,G]; " 7-segment LED display CLK DQ !Q Q0.D = !Q0 Q0 Q0.D !Q0 Registered Buffer output

12. div2cnt.abl (cont’d) CLK DQ !Q Q0.D = !Q0 Q0 Q0.D !Q0 EQUATIONS Q0.c = PB; Q0.d = !Q0; DP = PB; " decimal point @radix 16; truth_table ( Q0 -> Segments ) " 7-segment display 0 -> 7E; 1 -> 30; END Div2Cnt Counts 0, 1, 0, 1 …

13. Registered Feedback in GAL16V8

14. GAL 16V8 D Flip-Flops On RESET Q is cleared to 0. Therefore, output pin is HIGH

15. Simulation File, div2cnt.si CUPL Simulation File

16. Simulation File, div2cnt.si Note: Power-on reset sets all outputs high. Therefore, first test vector MUST go LOW. CUPL Simulation File

17. CUPL Simulation Output

18. A 1-Bit Register