Presentation is loading. Please wait.

Presentation is loading. Please wait.

1 Logic design of asynchronous circuits Part II: Logic synthesis from concurrent specifications.

Published by Modified over 9 years ago

Similar presentations

Presentation on theme: "1 Logic design of asynchronous circuits Part II: Logic synthesis from concurrent specifications."— Presentation transcript:

1 1 Logic design of asynchronous circuits Part II: Logic synthesis from concurrent specifications

2 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits2 Outline Overview of the synthesis flow Specification State graph and next-state functions State encoding Implementability conditions Speed-independent circuit –Complex gates –C-element architecture

3 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits3 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

4 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits4 x y z x+ x- y+ y- z+ z- Signal Transition Graph (STG) x y z Specification

5 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits5 x y z x+ x- y+ y- z+ z- Token flow

6 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits6 x+ x- y+ y- z+ z- xyz 000 x+ 100 y+ z+ y+ 101 110 111 x- 001 011 y+ z- 010 y- State graph

7 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits7 Next-state functions xyz 000 x+ 100 y+ z+ y+ 101 110 111 x- 001 011 y+ z- 010 y-

8 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits8 x z y Gate netlist

9 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits9 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

10 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits10 VME bus Device LDS LDTACK D DSr DSw DTACK VME Bus Controller Data Transceiver Bus DSr LDS LDTACK D DTACK Read Cycle

11 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits11 STG for the READ cycle LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDS LDTACK D DSr DTACK VME Bus Controller

12 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits12 Choice: Read and Write cycles DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK-DTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

13 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits13 Choice: Read and Write cycles DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

14 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits14 Choice: Read and Write cycles DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

15 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits15 Choice: Read and Write cycles DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

16 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits16 Circuit synthesis Goal: –Derive a hazard-free circuit under a given delay model and mode of operation

17 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits17 Speed independence Delay model –Unbounded gate / environment delays –Certain wire delays shorter than certain paths in the circuit Conditions for implementability: –Consistency –Complete State Coding –Persistency

18 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits18 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

19 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits19 STG for the READ cycle LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDS LDTACK D DSr DTACK VME Bus Controller

20 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits20 Binary encoding of signals DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS+

21 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits21 Binary encoding of signals DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS+ 10000 10010 10110 0111001110 01100 00110 10110 (DSr, DTACK, LDTACK, LDS, D)

22 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits22 QR (LDS+) QR (LDS-) Excitation / Quiescent Regions ER (LDS+) ER (LDS-) LDS- LDS+ LDS-

23 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits23 Next-state function 0  1 LDS- LDS+ LDS- 1  0 0  0 1  1 10110

24 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits24 Karnaugh map for LDS DTACK DSr D LDTACK 00011110 00 01 11 10 DTACK DSr D LDTACK 00011110 00 01 11 10 LDS = 0 LDS = 1 01-0 000000/1? 1 111 - - - --- ---- - ---- ---

25 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits25 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

26 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits26 Concurrency reduction LDS- LDS+ LDS- 10110 DSr+

27 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits27 Concurrency reduction LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+

28 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits28 State encoding conflicts LDS- LDTACK- LDTACK+ LDS+ 10110

29 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits29 Signal Insertion LDS- LDTACK- D- DSr- LDTACK+ LDS+ CSC- CSC+ 101101 101100

30 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits30 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Design flow

31 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits31 Complex-gate implementation

32 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits32 Implementability conditions Consistency –Rising and falling transitions of each signal alternate in any trace Complete state coding (CSC) –Next-state functions correctly defined Persistency –No event can be disabled by another event (unless they are both inputs)

33 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits33 Implementability conditions Consistency + CSC + persistency There exists a speed-independent circuit that implements the behavior of the STG (under the assumption that ay Boolean function can be implemented with one complex gate)

34 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits34 Persistency 100000001 a- c+ b+b+ b+b+ a c b a c b is this a pulse ? Speed independence  glitch-free output behavior under any delay

35 a+ b+ c+ d+ a- b- d- a+ c-a- 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+

36 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ ab cd 00011110 00 01 11 10 1 11 11 1 0 0000 ER(d+) ER(d-)

37 ab cd 00011110 00 01 11 10 1 11 11 1 0 0000 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ Complex gate

38 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits38 Implementation with C elements C R S z  S+  z+  S-  R+  z-  R-  S (set) and R (reset) must be mutually exclusive S must cover ER(z+) and must not intersect ER(z-)  QR(z-) R must cover ER(z-) and must not intersect ER(z+)  QR(z+)

39 ab cd 00011110 00 01 11 10 1 11 11 1 0 0000 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d

40 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d but...

41 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d Assume that R=ac has an unbounded delay Starting from state 0000 (R=1 and S=0): a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ; R+ disabled (potential glitch)

42 ab cd 00011110 00 01 11 10 1 11 11 1 0 0000 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d Monotonic covers

43 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits43 C-based implementations C S R d C d a b c a b c d weak a c d generalized C elements (gC) weak

44 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits44 Speed-independent implementations Implementability conditions –Consistency –Complete state coding –Persistency Circuit architectures –Complex (hazard-free) gates –C elements with monotonic covers –...

45 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits45 Synthesis exercise y- z-w- y+x+ z+ x- w+ 1011 0111 0011 1001 1000 1010 0001 00000101 00100100 0110 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ Derive circuits for signals x and z (complex gates and monotonic covers)

46 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits46 Synthesis exercise 1011 0111 0011 1001 1000 1010 0001 00000101 00100100 0110 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ wx yz 00011110 00 01 11 10 - - - - Signal x 1 0 1 1 1 1 1 0 0 0 0 0

47 ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits47 Synthesis exercise 1011 0111 0011 1001 1000 1010 0001 00000101 00100100 0110 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ wx yz 00011110 00 01 11 10 - - - - Signal z 1 0 0 0 0 1 1 1 0 0 0 0

Download ppt "1 Logic design of asynchronous circuits Part II: Logic synthesis from concurrent specifications."

Similar presentations

Delay models (I) A B C Real (analog) behaviorAbstract behavior A B C Abstractions are necessary to define delay models manageable for design, synthesis.

Delay models (I) A B C Real (analog) behaviorAbstract behavior A B C Abstractions are necessary to define delay models manageable for design, synthesis.
CS370 – Spring 2003 Hazards/Glitches. Time Response in Combinational Networks Gate Delays and Timing Waveforms Hazards/Glitches and How To Avoid Them.

CS370 – Spring 2003 Hazards/Glitches. Time Response in Combinational Networks Gate Delays and Timing Waveforms Hazards/Glitches and How To Avoid Them.
Andrey Mokhov, Victor Khomenko Danil Sokolov, Alex Yakovlev Dual-Rail Control Logic for Enhanced Circuit Robustness.

Andrey Mokhov, Victor Khomenko Danil Sokolov, Alex Yakovlev Dual-Rail Control Logic for Enhanced Circuit Robustness.
ECE 3110: Introduction to Digital Systems

ECE 3110: Introduction to Digital Systems
1 BalsaOpt a tool for Balsa Synthesis Francisco Fernández-Nogueira, UPC (Spain) Josep Carmona, UPC (Spain)

1 BalsaOpt a tool for Balsa Synthesis Francisco Fernández-Nogueira, UPC (Spain) Josep Carmona, UPC (Spain)
1 Advanced Digital Design Synthesis of Control Circuits by A. Steininger and J. Lechner Vienna University of Technology.

1 Advanced Digital Design Synthesis of Control Circuits by A. Steininger and J. Lechner Vienna University of Technology.
Hazard-free logic synthesis and technology mapping I Jordi Cortadella Michael Kishinevsky Alex Kondratyev Luciano Lavagno Alex Yakovlev Univ. Politècnica.

Hazard-free logic synthesis and technology mapping I Jordi Cortadella Michael Kishinevsky Alex Kondratyev Luciano Lavagno Alex Yakovlev Univ. Politècnica.
Hardware and Petri nets Synthesis of asynchronous circuits from Signal Transition Graphs.

Hardware and Petri nets Synthesis of asynchronous circuits from Signal Transition Graphs.
Logic Decomposition of Asynchronous Circuits Using STG Unfoldings Victor Khomenko School of Computing Science, Newcastle University, UK.

Logic Decomposition of Asynchronous Circuits Using STG Unfoldings Victor Khomenko School of Computing Science, Newcastle University, UK.
Direct synthesis of large-scale asynchronous controllers using a Petri-net-based approach Ivan BlunnoPolitecnico di Torino Alex BystrovUniv. Newcastle.

Direct synthesis of large-scale asynchronous controllers using a Petri-net-based approach Ivan BlunnoPolitecnico di Torino Alex BystrovUniv. Newcastle.
Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT Victor Khomenko, Maciej Koutny, and Alex Yakovlev University.

Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT Victor Khomenko, Maciej Koutny, and Alex Yakovlev University.
ECE 331 – Digital System Design Introduction to and Analysis of Sequential Logic Circuits (Lecture #20) The slides included herein were taken from the.

ECE 331 – Digital System Design Introduction to and Analysis of Sequential Logic Circuits (Lecture #20) The slides included herein were taken from the.
Detecting State Coding Conflicts in STGs Using Integer Programming Victor Khomenko, Maciej Koutny, and Alex Yakovlev University of Newcastle upon Tyne.

Detecting State Coding Conflicts in STGs Using Integer Programming Victor Khomenko, Maciej Koutny, and Alex Yakovlev University of Newcastle upon Tyne.
Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel.

Hardware and Petri nets: application to asynchronous circuit design Jordi CortadellaUniversitat Politècnica de Catalunya, Spain Michael KishinevskyIntel.
Introduction to asynchronous circuit design: specification and synthesis Jordi Cortadella, Universitat Politècnica de Catalunya, Spain Michael Kishinevsky,

Introduction to asynchronous circuit design: specification and synthesis Jordi Cortadella, Universitat Politècnica de Catalunya, Spain Michael Kishinevsky,
Introduction to asynchronous circuit design: specification and synthesis Part IV: Synthesis from HDL Other synthesis paradigms.

Introduction to asynchronous circuit design: specification and synthesis Part IV: Synthesis from HDL Other synthesis paradigms.
Introduction to asynchronous circuit design: specification and synthesis Part III: Advanced topics on synthesis of control circuits from STGs.

Introduction to asynchronous circuit design: specification and synthesis Part III: Advanced topics on synthesis of control circuits from STGs.
Asynchronous Sequential Logic

Asynchronous Sequential Logic
Introduction to asynchronous circuit design: specification and synthesis Part II: Synthesis of control circuits from STGs.

Introduction to asynchronous circuit design: specification and synthesis Part II: Synthesis of control circuits from STGs.
Combining Decomposition and Unfolding for STG Synthesis (application paper) Victor Khomenko 1 and Mark Schaefer 2 1 School of Computing Science, Newcastle.

Combining Decomposition and Unfolding for STG Synthesis (application paper) Victor Khomenko 1 and Mark Schaefer 2 1 School of Computing Science, Newcastle.

Similar presentations

Ads by Google