1. UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory UC San Diego Computer Engineering VLSI CAD Laboratory Basic Ideas Gate-length biasing implies increasing the gate-length by 5%-10%. Impact of gate-length biasing: Leakage reduces exponentially Delay increases linearly Impact on leakage variability Gate-length biasing reduces leakage and its variability, however, with a delay penalty Solution: Selectively bias devices that are non-critical to circuit performance  Reduction of leakage and its variability with no or very small delay penalty Gate-length biasing implies increasing the gate-length by 5%-10%. Impact of gate-length biasing: Leakage reduces exponentially Delay increases linearly Impact on leakage variability Gate-length biasing reduces leakage and its variability, however, with a delay penalty Solution: Selectively bias devices that are non-critical to circuit performance  Reduction of leakage and its variability with no or very small delay penalty Gate-Length Leakage Gate-Length Biasing A Highly Manufacturable Approach to Leakage Control To appear in Design Automation Conference, 2004 ( http://vlsicad.ucsd.edu ) Puneet Sharma (sharma@ucsd.edu) Advisor: Prof. Andrew B. Kahng Jointly with Mr. Puneet Gupta Electrical & Computer Engineering Introduction With process scaling, leakage power reduction has become one of the most important design goals. In this research, we study the efficacy and feasibility of using a marginally increased gate-length for leakage reduction. Delay increases linearly and leakage decreases exponentially as gate- length increases. We utilize this fact to propose the use of an increased gate-length for non-critical devices in a circuit. Application of this technique results in reduced leakage while having very small impact on circuit performance. Unlike the Multi-V t approach, which is highly effective and used in practice, the proposed approach does not require additional process steps and can be applied anytime during the design cycle. Gate-length biasing also drastically reduces leakage variability which is one of the key challenges facing the silicon industry. Initial results show up to 23% leakage reduction with only a 2% delay penalty. Leakage variability due to inter-die process variations reduces by up to 54%. With process scaling, leakage power reduction has become one of the most important design goals. In this research, we study the efficacy and feasibility of using a marginally increased gate-length for leakage reduction. Delay increases linearly and leakage decreases exponentially as gate- length increases. We utilize this fact to propose the use of an increased gate-length for non-critical devices in a circuit. Application of this technique results in reduced leakage while having very small impact on circuit performance. Unlike the Multi-V t approach, which is highly effective and used in practice, the proposed approach does not require additional process steps and can be applied anytime during the design cycle. Gate-length biasing also drastically reduces leakage variability which is one of the key challenges facing the silicon industry. Initial results show up to 23% leakage reduction with only a 2% delay penalty. Leakage variability due to inter-die process variations reduces by up to 54%. Gate-Length Biasing Methodology Granularity: Freedom to assign different biased gate-lengths to different devices. We consider three options: 1.Technology Level All devices in the library have the same biased gate-length. 2.Cell Level All devices in a cell have the same biased gate-length. Devices in different cells may have different biased gate-lengths. 3.Device Level All devices are free to have an independent biased gate-length. Our simplified device-level approach – for each cell, NMOS devices have one biased gate-length and PMOS devices have an independent biased gate-length. Devices In different cells have independent biased gate-lengths. Biased Gate-Length: How much to bias devices by? Constrained to less than 10% to preserve layout pin-compatibility Delay penalty constraint imposed and maximum biasing done subject to it Smart Cell Selector We perform a simple leakage to area mapping and then use an area optimizer (Synopsys Design Compiler) to minimize area (leakage). Granularity: Freedom to assign different biased gate-lengths to different devices. We consider three options: 1.Technology Level All devices in the library have the same biased gate-length. 2.Cell Level All devices in a cell have the same biased gate-length. Devices in different cells may have different biased gate-lengths. 3.Device Level All devices are free to have an independent biased gate-length. Our simplified device-level approach – for each cell, NMOS devices have one biased gate-length and PMOS devices have an independent biased gate-length. Devices In different cells have independent biased gate-lengths. Biased Gate-Length: How much to bias devices by? Constrained to less than 10% to preserve layout pin-compatibility Delay penalty constraint imposed and maximum biasing done subject to it Smart Cell Selector We perform a simple leakage to area mapping and then use an area optimizer (Synopsys Design Compiler) to minimize area (leakage). Experimental Results Device level leakage reduction Circuit level leakage reduction To highlight the real value, we also use gate-length biasing in conjunction with Multi-V t leakage minimization technique. Leakage variability reduction Layout pin-compatibility is preserved  Described technique can be applied as a post P&R step Mentor Calibre used to verify that process variability does not “absorb” gate-length biasing Device level leakage reduction Circuit level leakage reduction To highlight the real value, we also use gate-length biasing in conjunction with Multi-V t leakage minimization technique. Leakage variability reduction Layout pin-compatibility is preserved  Described technique can be applied as a post P&R step Mentor Calibre used to verify that process variability does not “absorb” gate-length biasing Ongoing Work 1.Construction of effective biasing based leakage optimization heuristics 2.Gate-length selection at true device-level granularity 3.Evaluation of gate-length biasing at future technology nodes 1.Construction of effective biasing based leakage optimization heuristics 2.Gate-length selection at true device-level granularity 3.Evaluation of gate-length biasing at future technology nodes Gate-Length Variability Biasing Overview Spice Model Spice Netlists Biased Gate-Length Granularity Characterize and augment standard cell library such that each master has a biased gate-length variant Extended Standard Cell Library Circuit Netlist Modified Netlist Dynamic + Leakage Power Estimate Smart Cell Selector Uses slower, low-leakage cells in non-critical paths Uses faster, high-leakage cells in critical paths Circuit delay penalty of less than 2.5% Leakage distribution for alu128 Percentage reduction in leakage spread Leakage Variability