1. EE466: VLSI Design 2009 Term Project

2. Expectation To introduce you to basic research ideas Involves reading research paper Extraction of relevant parameters Simulation of circuits Presentation of results

3. Low Swing Signaling Ideas –Low Swing Signaling Reasons? –Crosstalk –Performance metrics –Power dissipation metrics

4. Low Swing Signaling Low Swing Interconnect Interface Circuits Hui Zhang & Jan Rabaey 2 Circuits to compare

5. Basic Idea Interface circuits

6. Interfaces Conventional Level Converter (CLC) –Reference Symmetric Source-Follower Driver with Level Converter (SSDLC) Level Converting Register (LCR)

7. CLC VddL is the low swing reference voltage Uses static devices

8. SSDLC Swing is limited between Vtn and Vdd-Vtn

9. LCR REF voltage limits the swing

10. Goals Simulate Circuits Consider a 3 wire bus –Apply similar interface circuits on neighbors –Study all crosstalk patterns –Evaluate average delay on victim –Evaluate worst case delay on victim Compute power and energy dissipation –Present energy delay product metrics

11. Milestones Reading Material –Papers for reading on website Design of interface circuits Understand wire parameter extraction –Reading material will be provided Technology and Reliability Constrained Copper Interconnects Part II: Performance Implications –Study crosstalk effects Present report with relevant metrics

12. Deadlines Final submission –Day of final exam