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Efficient Associative SIMD Processing for Non-Tabular Data Jalpesh K. Chitalia and Robert A. Walker Computer Science Department Kent State University
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Presentation Outline ASC Processor Architecture Associative Features Structure Codes Represent Data Structures Structure Code Operations Summary and Future Work
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The ASC Processor A scalable design implemented on a million gate Altera FPGA SIMD-like architecture Currently, 36 8-bit Processing Elements (PE) available 8-bit Instruction Stream (IS) control unit with 8-bit Instruction and Data addresses, 32-bit instructions
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The ASC Architecture
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Each PE listens to the IS through the broadcast and reduction network PEs can communicate amongst themselves using the PE Network PE may either execute or ignore the microcode instruction broadcast by IS under the control of the Mask Stack
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The ASC Features Associative Search Each PE can search its local memory for a key under the control of IS Responder Resolution A special circuit signals if ‘at least one’ record was found Masked Operation Local Mask Stacks can turn on or off the execution of instruction from IS
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The ASC Example Select * from Students where Grade > 90
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The ASC Features Constant Time Associative Operations Associative Search Finding minimum or maximum in a field Ideal for Database processing Data is organized in tabular format Each tuple in a table can be processed by one PE PE Network Many parallel algorithms require all PEs to move contents in a regular pattern E.g.: Image Convolution, Matrix Multiplication
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Non Tabular Data Structures Many applications use linked list based data structures For example, plain HTML parsing can be done using tree-structure Similarly, XML or Object-relational databases can be represented using trees only Game programming uses tree-based algorithms, and demand much of processing power Complier construction uses directed acyclic graphs and tree structures
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Data Structure Codes A unique coding scheme Allows representation of any data structure into a tabular format Tabular format allows division of data amongst the PEs Also known as “structure code” Different coding schemes for different data structures Uses Associative Search feature of the ASC Processor
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Simple List-based Structures The left figure shows a possible representation of 1D and 2D arrays. Representations of this kind should be particularly useful for adjacency matrix or sparse matrix The right figure represents stack and queue, depending on the use of appropriate functions
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Complex List-based Structures Each digit-position indicates the level of a tree Each value in that position indicates the position of that child from the left Discussions henceforth are confined to trees Graphs are read in a slightly different manner
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Structure Code Operations Two sets of constant-time operations: scalar and parallel Scalar Instructions are simple mathematic operations Search parent, child or root Finds value of structure code for next or previous nodes Parallel Instructions use complex associative operations Finds code for next, previous or both siblings ‘Locates’ the required node for further processing
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Scalar Operations fstcd: leftmost child nxtcd: right sibling prvcd: left sibling trncd: truncate (parent) node trnacd: truncate all (root) node Can be used to allocate a new node Limited use in searching records
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Parallel Operations Index instructions: Flags a node of the result to ease further processing nxtdex (next or right), prvdex (previous or left) and sibdex (siblings or both left and right) Value instructions: Returns the exact structure code of the result nxtval (next or right) and prvval (previous or left) Can be used to ‘locate’ nodes in any tree Uses parallel and associative hardware resources
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Summary SIMD-based computers are more suited for database processing ASC processor with its associative operations makes them more efficient Structure codes translate non-tabular data structures into a tabular format Tree and Graphs can be represented and evenly divided like records in a table Object-relational databases, XML databases, plain HTML processing Stacks, Queues, multi-dimensional arrays can be represented Structure codes not required for even division
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Future Work Efforts are in place to clean the architecture To allow multiplier/divider on each PE To accommodate RISC instruction set Unpacked bytes are used to support variable-length structure code Can be avoid with an efficient divider unit Developing applications that use structure codes
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Questions? Thank You!
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