1. ECE 667 - Synthesis & Verification - Lecture 3 1 ECE 697B (667) Spring 2006 ECE 697B (667) Spring 2006 Synthesis and Verification of Digital Circuits Scheduling Algorithms Analytical approach - ILP

2. ECE 667 - Synthesis & Verification - Lecture 3 2 Scheduling – a Combinatorial Optimization Problem NP-complete ProblemNP-complete Problem Optimal solutions for special cases and ILPOptimal solutions for special cases and ILP –Integer linear program (ILP) –Branch and bound HeuristicsHeuristics –iterative Improvements, constructive Various versions of the problemVarious versions of the problem Unconstrained minimum latencyUnconstrained minimum latency Resource-constrained minimum latencyResource-constrained minimum latency Timing constrained minimum latencyTiming constrained minimum latency Latency-constrained minimum resourcesLatency-constrained minimum resources If all resources are identical, problem is reduced to multiprocessor scheduling (Hu’s algorithm)If all resources are identical, problem is reduced to multiprocessor scheduling (Hu’s algorithm) Minimum latency multiprocessor problem is intractable under resource constraintMinimum latency multiprocessor problem is intractable under resource constraint

3. ECE 667 - Synthesis & Verification - Lecture 3 3 Integer Linear Programming Given : integer-valued matrix A m x n vectors: B = ( b 1, b 2, …, b m ) and C = ( c 1, c 2, …, c n ) Minimize: C T X subject to: A X  B X = ( x 1, x 2, …, x n ) is an integer-valued vector

4. ECE 667 - Synthesis & Verification - Lecture 3 4 Integer Linear Programming - Scheduling Problem ( simple version) Assumption : identical computations, each computation takes one cycle For a set of (dependent) computations {v 1,v 2,...,v n }, find the minimum number of units needed to complete the execution in k control steps (MR-LCS problem) Integer Linear Programming (ILP): – –Let y 0 be an integer variable (# units to be minimized) – –for each control step l =1, …, k, define variable x i l as x i l = 1, if computation v i is executed in the l -th control step x il = 0, otherwise – –define variable y l ( number of units in control step l ) y l = x 1 l + x 2 l +... + x n l =  i x i l

5. ECE 667 - Synthesis & Verification - Lecture 3 5 ILP Scheduling For each precedence relation: – –If v j has to be executed after v i - introduce dependency constraint : x j1 + 2 x j2 +... + k x jk  x i1 + 2 x i2 +... + k x ik + d(i) ( for unit delay, d(i) = 1) Minimize: y 0 Subject to: x j1 + x j2 +...+ x jk = 1 for all j = 1,…, n (computations) y l  y 0 for all l = 1,…, k (steps) 1 st constraint: each computation v i can start only once: x i l = 1 for only one value of l (control step) Meaning of y 0 : upper bound on the number of units, to be minimized

6. ECE 667 - Synthesis & Verification - Lecture 3 6 Example 1 - Formulation n = 6 computations k = 3 control steps v1v1 v2v2 v3v3 v4v4 v6v6 v5v5 Dependency constraints: e.g. v 4 executes after v 1 x 41 + 2x 42 + 3x 43  x 11 + 2x 12 + 3x 13 +1....... etc. Resource constraints: y l = x 1l + x 2l + x 3l + x 4l + x 5l + x 6l for l = 1,…, 3 (steps) Execution constraints: x i1 + x i2 + x i3 = 1 for i = 1,…, 6

7. ECE 667 - Synthesis & Verification - Lecture 3 7 Example 1 - Solution Minimize: y 0 Subject to: y l  y 0 for all l = 1,…, 3 Dependency constraints … Execution constraints … One solution: y 0 = 2 x 11 = 1, x 21 = 1, x 32 = 1, x 42 = 1, x 53 = 1, x 63 = 1. all other x i l = 0 v1v1 v2v2 v3v3 v4v4 v6v6 v5v5

8. ECE 667 - Synthesis & Verification - Lecture 3 8 ILP Model of Scheduling Binary decision variables x il x i l = 1 if operation v i starts in step l i = 0, 1, …, n (operations) l = 1, 2, …  +1 (steps, with limit ) Start time is unique:  l x il =  x il l=t i S l=t i L where: t i S = time of operation I computed with ASAP t i L = time of operation I computed with ALAP Note: Start time for v i :

9. ECE 667 - Synthesis & Verification - Lecture 3 9 ILP Model of Scheduling (contd.) Precedence relationships must be satisfied Resource bounds must be met – –let upper bound on number of resources of type k be a k

10. ECE 667 - Synthesis & Verification - Lecture 3 10 Minimum-latency Scheduling under Resource-constraints Let t be the vector whose entries are start times Formal ILP model

11. ECE 667 - Synthesis & Verification - Lecture 3 11 Example 2 – Multiple Resources Two types of resources – –Multiplier – –ALU Adder Subtraction Comparison Both take 1 cycle of execution time

12. ECE 667 - Synthesis & Verification - Lecture 3 12 Example 2 (contd.) Heuristic (list scheduling) gives latency = 4 stepsHeuristic (list scheduling) gives latency = 4 steps Use ALAP and ASAP (with no resource constraints) to get bounds on start timesUse ALAP and ASAP (with no resource constraints) to get bounds on start times –ASAP matches latency of heuristic (so heuristic is optimum)(so heuristic is optimum) Constraints?Constraints?

13. ECE 667 - Synthesis & Verification - Lecture 3 13 Example 2 (contd.) Start time must be unique  l x il =  x il l=t i S l=t i L where: t i S = time of operation i computed with ASAP t i L = time of operation i computed with ALAP Recall:

14. ECE 667 - Synthesis & Verification - Lecture 3 14 Example 2 (contd.) Precedence constraints – –Note: only non-trivial ones listed (those with more than one possible start time for at least one operation)

15. ECE 667 - Synthesis & Verification - Lecture 3 15 Example 2 (contd.) Resource constraints MULT a1=2 ALU a2=2

16. ECE 667 - Synthesis & Verification - Lecture 3 16 Example 2 (contd.) Consider c = [0, 0, …, 1] T – –Minimum latency schedule – –since sink has no mobility (x n,5 = 1), any feasible schedule is optimum Consider c = [1, 1, …, 1] T – –finds earliest start times for all operations  i  l – –or equivalently:

17. ECE 667 - Synthesis & Verification - Lecture 3 17 Example Solution 2: Optimum Schedule Under Resource Constraint

18. ECE 667 - Synthesis & Verification - Lecture 3 18 Example 3 Assume multiplier costs 5 units of area, and ALU costs 1 unit of area Same uniqueness and sequencing constraints as before Resource constraints are in terms of unknown variables a 1 and a 2 a 1 = number of multipliers a 2 = number of ALUs (add/sub)

19. ECE 667 - Synthesis & Verification - Lecture 3 19 Example 3 (contd.) Resource constraints MULT ALU

20. ECE 667 - Synthesis & Verification - Lecture 3 20 Example 3 - Solution Minimize c T a = 5.a 1 + 1.a 2 Solution with cost = 12

21. ECE 667 - Synthesis & Verification - Lecture 3 21 Precedence-constrained Multiprocessor Scheduling All operations performed by the same type of resourceAll operations performed by the same type of resource –intractable problem; even if operations have unit delay