1. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt1 Lecture 9alt Combinational ATPG (A Shortened version of Original Lectures 9-12) n ATPG problem n Algorithms Multi-valued algebra D-algorithm Podem n ATPG system n Summary n Exercise

2. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt2 ATPG Problem n ATPG: Automatic test pattern generation Given n A circuit (usually at gate-level) n A fault model (usually stuck-at type) Find n A set of input vectors to detect all modeled faults. n Core problem: Find a test vector for a given fault. n Combine the “core solution” with a fault simulator into an ATPG system.

3. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt3 What is a Test? X100101XXX100101XX Stuck-at-0 fault 1/0 Fault activation Path sensitization Primary inputs (PI) Primary outputs (PO) Combinational circuit 1/0 Fault effect

4. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt4 ATPG is a Search Problem n Search the input vector space for a test: n Initialize all signals to unknown (X) state – complete vector space is the playing field n Activate the given fault and sensitize a path to a PO – narrow down to one or more tests XXXXXX sa1 Circuit Vector Space X01X01 sa1 Circuit Vector Space 0/1 001101

5. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt5 Need to Deal With Two Copies of the Circuit X01X01 Good circuit 0 X01X01 sa1 Faulty circuit 1 X01X01 sa1 Circuit 0/1 Alternatively, use a multi-valued algebra of signal values for both good and faulty circuits. Same input Different outputs X X X

6. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt6 Multiple-Valued Algebras Symbol D 0 1 X G0 G1 F0 F1 Alternative Representation 1/0 0/1 0/0 1/1 X/X 0/X 1/X X/0 X/1 Faulty Circuit 0 1 0 1 X 0 1 Fault-free circuit 1 0 1 X 0 1 X Roth’s Algebra Muth’s Additions

7. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt7 Function of NAND Gate c Input a 01XD 011111 110XD X1XXXX D1X1 1DX1D D D D D D a b c D 1/0 0/1 D 1 Input b

8. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt8 D-Algorithm (Roth et al., 1967, D-alg II) n Use D-algebra n Activate fault n Place a D or D at fault site n Do justification, forward implication and consistency check for all signals n Repeatedly propagate D-chain toward POs through a gate n Do justification, forward implication and consistency check for all signals n Backtrack if n A conflict occurs, or n D-frontier becomes a null set n Stop when n D or D at a PO, i.e., test found, or n If search exhausted without a test, then no test possible

9. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt9 Definitions n Justification: Changing inputs of a gate if the present input values do not justify the output value. n Forward implication: Determination of the gate output value, which is X, according to the input values. n Consistency check: Verifying that the gate output is justifiable from the values of inputs, which may have changed since the output was determined. n D-frontier: Set of gates whose inputs have a D or D, and the output is X.

10. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt10 Definition: Singular Cover n A singular cover defines the least restrictive inputs for a deterministic output value. n Used for: n Line justification: determine gate inputs for specified output. n Forward implication: determine gate output. a b c Singular covers abc SC-10X1 SC-2X01 SC-3110 XXXX 0 Examples:XX0 ∩ 110 = 110 0XX ∩ 0X1 = 0X1

11. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt11 Definition: D-Cubes n D-cubes are singular covers with five-valued signals n Used for D-drive (propagation of D through gates) and forward implication. D-cubeabc D-1D1 D-21D D-31D D-41D D-5DD D-6D D-7D01 D-80D1 D-9D1 D-10D1 D D D D D D D D D a b c XDXD X Examples:XDX ∩ 1DD = 1DD 0DX ∩ 0D1 = 0D1 DDX ∩ DD1 = DD1

12. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt12 D-Intersection ∩01XD 000 111 X01XD DDD D D D D Undefined State (conflict) D

13. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt13 An Example: XOR a b a2 a1 b1 b2 c1 c c2 d e f Find tests for:c sa0 c1 sa0 c2 sa0

14. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt14 XOR: Test for c sa0 a b a2 a1 b1 b2 c1 c c2 d e f ActionOperationD-frontier 1.Activate faultc=1 or c=c1=c2=Dd, e 2.Justify c=1XX1 ∩ 0X1 = 0X1, a=a1=a2=0d, e 3.Forward impl a2=00DX ∩ 0D1= 0D1, d=1e 4.Forward imp d=11XX ∩ XXX= 1XX, no implication possiblee 5.D-drive c2→eDXX ∩ D1D= D1D, b2=b=b1=1, e=Df 6.Forward impl b1=1011 ∩ 0X1 = 011, consistency checkedf 7.D-drive e→f1DX ∩ 1DD = 1DD, f=DPO 8.Stop, test foundTest: (a,b) = (0, 1), f = 1

15. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt15 Finding Other Detected Faults by the Generated Test n Use any fault simulator: n Serial n Deductive n Concurrent n Other n Test-Detect: A simple fault simulation algorithm n Uses true-value simulation n Uses D-algebra for fault analysis n Roth et al., 1967

16. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt16 Test-Detect: XOR, Test (0,1) n Determine good circuit signal values. n For each fault n Place a D or D at the fault site n Perform forward implications n Fault is detected if any PO assumes a D or D value a b a2 a1 b1 b2 c1 c c2 d e f 0101 1 0 1 1 b1 b2 D for c1 sa0 D for c2 sa0 D D 0DX ∩ 0D1 = 0D1 (null D-frontier) → c1 sa0 not detected D1X ∩ D1D = D1D 1DX ∩ 1DD = 1DD, D at PO → c2 sa0 is detected

17. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt17 XOR: Test for c1 sa0 a b a2 a1 b1 b2 c1 c c2 d e f ActionOperationD-frontier 1.Activate faultc1=1 or c=c2=1, c1=Dd 2.Justify c=1XX1 ∩ 0X1 = 0X1, a=a1=a2=0 d 3.Forward impl a2=00DX ∩ 0D1= 0D1, d=1null 4.Back-up, redo step 3No choice availablenull 5.Back-up, redo step 2XX1 ∩ X01 = X01, b=b1=b2=0, a=X, d=Xd 6.Forward impl b2=010X ∩ X01 = 101, e=1d 7.Forward impl e=1X1X ∩ XXX = X1X, no implication possibled 8.D-drive c1→dXDX ∩ 1DD= 1DD, a2=a=a1=1,d=Df 9.Forward impl a1=1101 ∩ X01 = 101, consistency checkedf 10.Forward impl d=DD1X ∩ D1D = D1D, f=DPO 11.Stop, test foundTest: (a,b) = (1, 0), f = 1

18. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt18 Complexity of D-Alg II n Signal values on all lines (PIs and internal lines) are manipulated using 5-valued algebra. n Worst-case combinations of signals that may be tried is 5 #lines n For XOR circuit, 5 12 = 244,140,625. n Podem: A reduced-complexity ATPG algorithm n Recognizes that internal signals depend on PIs. n Only PIs are independent variables and should be manipulated. n Because faults are internal, a PI can assume only 3 values (0, 1, X). n Worst-case combinations = 3 #PI ; for XOR circuit, 3 2 = 8.

19. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt19 Podem (Goel, 1981) n Podem: Path oriented decision making n Step 1: Define an objective (fault activation, D-drive, or line justification) n Step 2: Backtrace from site of objective to PIs (use testability measure guidance) to determine a value for a PI n Step 3: Simulate logic with new PI value n If objective not accomplished but is possible, then continue backtrace to another PI (step 2) n If objective accomplished and test not found, then define new objective (step 1) n If objective becomes impossible, try alternative backtrace (step 2) n Use X-PATH-CHECK to test whether D-frontier still there – a path of X’s from a D-frontier to a PO must exist.

20. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt20 XOR Example Again (1,1)6 (3,2)5 (4,2)3 (5,5)0 6 6 5 5 Compute SCOAP testability measures: (CC0,CC1)CO 7 7

21. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt21 Podem: Objective and Backtrace (1,1)6 (3,2)5 (4,2)3 (5,5)0 6 6 5 5 sa0 1. Objective 1: set fault site to 1 0 2&3. Backtrace to a PI and simulate 1 1 D X-path check fails → Back up: Erase effects of steps 2&3 Try alternative backtrace 7 7

22. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt22 Podem: Back up (1,1)6 (3,2)5 (4,2)3 (5,5)0 6 6 5 5 sa0 1. Objective 1: set fault site to 1 0 4&5. Alt. backtrace to a PI and simulate 1 1 D X-path check: OK Objective 1 achieved X-path 7 7

23. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt23 Podem: D-Drive (1,1)6 (3,2)5 (4,2)3 (5,5)0 6 6 5 5 sa0 4. Objective 2: D-drive, set line to 1 1 5. Backtrace to a PI and simulate 1 1 D 1 D D 0 D at PO →Test found 7 7

24. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt24 Another Podem Example (9, 2) S-a-1 1. Objective “0” 0 2. Backtrace “A=0” 3. Logic simulation for A=0 4. Objective possible but not accomplished

25. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt25 Podem Example (Cont.) (9, 2) S-a-1 1. Objective “0” 0 5. Backtrace “B=0” 6. Logic simulation for A=0, B=0 7. Objective possible but not accomplished 0 0 0

26. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt26 Podem Example (Cont.) (9, 2) S-a-1 1. Objective “0” 0 8. Backtrace “E=0” 9. Logic simulation for E=0 10. Objective possible but not accomplished 0 0 0 0 0

27. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt27 Podem Example (Cont.) (9, 2) S-a-1 1. Objective “0” 0 11. Backtrace “D=0” 12. Logic simulation for D=0 13. Objective accomplished 0 0 0 0 0 0 0

28. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt28 An ATPG System Random pattern generator Fault simulator Fault coverage improved? Random patterns effective? Save patterns Deterministic ATPG (D-alg. or Podem) yes no yes no Compact vectors Coverage Sufficient? no yes

29. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt29 Random-Pattern Generation n Easily gets tests for 60-80% of faults n Then switch to D-algorithm, Podem, or other ATPG method

30. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt30 Vector Compaction n Objective: Reduce the size of test vector set without reducing fault coverage. n Simulate faults with test vectors in reverse order of generation n ATPG patterns go first n Randomly-generated patterns go last (because they may have less coverage) n When coverage reaches 100% (or the original maximum value), drop remaining patterns n Significantly shortens test sequence – testing cost reduction. n Fault simulator is frequently used for compaction. n Many recent (improved) compaction algorithms.

31. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt31 Static and Dynamic Compaction of Sequences n Static compaction n ATPG should leave unassigned inputs as X n Two patterns compatible – if no conflicting values for any PI n Combine two tests t a and t b into one test t ab = t a ∩ t b using intersection n Detects union of faults detected by t a and t b n Dynamic compaction n Process every partially-done ATPG vector immediately n Assign 0 or 1 to PIs to test additional faults

32. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt32 Compaction Example n t 1 = 0 1 X t 2 = 0 X 1 t 3 = 0 X 0 t 4 = X 0 1 n Combine t 1 and t 3, then t 2 and t 4 n Obtain: t 13 = 0 1 0 t 24 = 0 0 1 n Test Length shortened from 4 to 2

33. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt33 Summary n Most combinational ATPG algorithms use D-algebra. n D-Algorithm is a complete algorithm: n Finds a test, or n Determines the fault to be redundant n Complexity is exponential in circuit size n Podem is another complete algorithm: n Works on primary inputs – search space is smaller than that of D-algorithm n Exponential complexity, but several orders faster than D- algorithm n More efficient algorithms available – FAN, Socrates, etc. n See, M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000, Chapter 7.

34. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt34 Exercise n For the circuit shown above n Determine SCOAP testability measures. n Derive a test for the stuck-at-1 fault at the output of the AND gate. n Using the parallel fault simulation algorithm, determine which of the four primary input faults are detectable by the test derived above.

35. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt35 Exercise: Answers (1,1) 4 (1,1) 3 (1,1) 4 (1,1) 3 (2,3) 2 (4,2) 0 ■ SCOAP testability measures, (CC0, CC1) CO, are shown below:

36. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt36 Exercise: Answers Cont. s-a-1 0 D D 0 0 ■ A test for the stuck-at-1 fault shown in the diagram is 00.

37. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 9alt37 Exercise: Answers Cont. PI1=0 PI2=0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 No fault PI1 s-a-0 PI1 s-a-1 PI2 s-a-0 PI2 s-a-1 PI2 s-a-1 detected ■ Parallel fault simulation of four PI faults is illustrated below. Fault PI2 s-a-1 is detected by the 00 test input.