1. Status – Week 249 Victor Moya

2. Summary MemoryController. MemoryController. Streamer. Streamer. TraceDriver. TraceDriver. Statistics. Statistics.

3. Memory Controller Added ‘request’ table. Added ‘request’ table. Added transaction identifier/ticket. Added transaction identifier/ticket. Allocated for each GPU unit (CP, Streamer). Allocated for each GPU unit (CP, Streamer). Should remove support for stride + data element size? -> Transaction(@, bytes). Should remove support for stride + data element size? -> Transaction(@, bytes).

4. Streamer Reimplemented. Reimplemented. Currently only stream mode supported (almost finished). Currently only stream mode supported (almost finished). Should be easier than in old implementation to add index mode (next week?). Should be easier than in old implementation to add index mode (next week?).

5. Streamer STREAMERRASTERIZER VERTEX SHADER ShaderCommand ConsumerState ShaderState ShaderOutput RasterizerState RasterizerInput

6. Streamer Uses small transactions: 1 attribute per transaction (up to 128 bits). Uses small transactions: 1 attribute per transaction (up to 128 bits). Define number of buses and bw with the Memory Controller: currently 2 bus (address + data) allows for a request per cycle and an attribute (or equivalent data) received per cycle. Define number of buses and bw with the Memory Controller: currently 2 bus (address + data) allows for a request per cycle and an attribute (or equivalent data) received per cycle.

7. Streamer Real world example: Real world example: R300: 4 vertex shaders, 256 bits DDR bus (512 bits from memory per cycle). R300: 4 vertex shaders, 256 bits DDR bus (512 bits from memory per cycle). Max. vertex ouput per cycle: 1 -> 4 DP4 for vector-matrix mul + 1 MOV for color (bypassed?)). Max. vertex ouput per cycle: 1 -> 4 DP4 for vector-matrix mul + 1 MOV for color (bypassed?)). Minimum attributes per vertex: position + color -> 256 bits. Minimum attributes per vertex: position + color -> 256 bits. For peak vertex throughput: 256 bit data bus with memory controller and two attributes requested per cycle (two address buses?). For peak vertex throughput: 256 bit data bus with memory controller and two attributes requested per cycle (two address buses?).

8. TraceDriver Almost ready to parse a simple (glBegin/glEnd) OpenGL trace. Almost ready to parse a simple (glBegin/glEnd) OpenGL trace. Start testing the GPU simulator next week? Start testing the GPU simulator next week?

9. Statistics Which statistics could be gathered with the current simulator? Which statistics could be gathered with the current simulator?