1. A.R. Hertneky J.W. O’Brien J.T. Shin C.S. Wessels Laser Controller One (LC1) www.teamvice.net

2. February 28, 2006Critical Design Review (CDR)2 Outline Background Architecture and parts Interfaces Circuit/logic design Updated schedule & responsibilities

3. February 28, 2006Critical Design Review (CDR)3 Laser Controller One (LC1) Interacts with laser analog control system Consists of rack- mountable enclosure with connections to external devices Will manage laser system to establish and maintain frequency lock

4. February 28, 2006Critical Design Review (CDR)4 Analog signals Saturated absorption spectroscopy (sat spec) raw signal is subject to high-pass filtering Derivatives can still be generated using a mixer Use sat spec (f 0 ) to update LCD Use first derivative (f 1 ) to locate peaks Use second derivative (f 2 ) to monitor lock f0f0 f1f1 f2f2

5. February 28, 2006Critical Design Review (CDR)5 System Environment Block Diagram

6. February 28, 2006Critical Design Review (CDR)6 Microprocessor Freescale M68EC020 Microprocessor Clock speed for… –wire wrapped prototype: 12MHz –PCB integration: 25MHz 32-bit data/24-bit address Dynamic bus sizing Instruction cache 100-QFP package

7. February 28, 2006Critical Design Review (CDR)7 Data Flow Block Diagram

8. February 28, 2006Critical Design Review (CDR)8 Memory Map StartEndPeripheral 0x0000000x0FFFFF Flash 0x1000000x1FFFFF SRAM 0x3000000x3FFFFF FPGA 0x4000000x40FFFF UARTs 0x4100000x41FFFF Counter/timers 0x4200000x42FFFF Key pad 0x4300000x43FFFF Shaft encoder 0x4400000x44FFFF LCD 0x4500000x45FFFF Digital I/O

9. February 28, 2006Critical Design Review (CDR)9 Control Flow Block Diagram

10. February 28, 2006Critical Design Review (CDR)10 Interrupt Priorities LevelPeripheral 7UART 1 6Counter/timer 1 5FPGA 4Key pad 3Counter/timer 2 2UART 2 1Shaft encoder

11. February 28, 2006Critical Design Review (CDR)11 CPLD Block Diagram

12. February 28, 2006Critical Design Review (CDR)12 Wire Wrap Prototype Preview clock/reset CPLD CPU Flash (x1) Headers for FPGA SRAM UARTs/ drivers

13. February 28, 2006Critical Design Review (CDR)13 Schematic: CPU

14. February 28, 2006Critical Design Review (CDR)14 Schematic: FPGA

15. February 28, 2006Critical Design Review (CDR)15 Schematic: Memory

16. February 28, 2006Critical Design Review (CDR)16 Schematic: UARTs

17. February 28, 2006Critical Design Review (CDR)17 Schematic: Keypad

18. February 28, 2006Critical Design Review (CDR)18 Schematic: RS-232 Drivers

19. February 28, 2006Critical Design Review (CDR)19 Schematic: LEDs

20. February 28, 2006Critical Design Review (CDR)20 Schematic: Shaft Encoder

21. February 28, 2006Critical Design Review (CDR)21 Schematic: Reset Circuit

22. February 28, 2006Critical Design Review (CDR)22 8 Channel/12 Bit Serial ADC - AD7890

23. February 28, 2006Critical Design Review (CDR)23 AD7890 A/D: Interfaces

24. February 28, 2006Critical Design Review (CDR)24 AD7890 A/D: Control Register

25. February 28, 2006Critical Design Review (CDR)25 AD7890 A/D: Timing Diagram

26. February 28, 2006Critical Design Review (CDR)26 Dual 12-Bit Serial DACPORT-AD7249

27. February 28, 2006Critical Design Review (CDR)27 AD7249 D/A Interfaces

28. February 28, 2006Critical Design Review (CDR)28 AD7890 D/A: Timing Diagram

29. February 28, 2006Critical Design Review (CDR)29 Software Architecture Message passing & synchronization will take place through circular buffers (CBs) Interrupt service routines (ISRs) will insert data in CBs Main program will setup hardware, and then begin checking for/acting on messages in CBs

30. February 28, 2006Critical Design Review (CDR)30 Software Flow Diagram Main Program Loop CBs ISRs Event UI Manager LCD Driver Laser Manager FPGA

31. February 28, 2006Critical Design Review (CDR)31 UI Mock-up

32. February 28, 2006Critical Design Review (CDR)32 Updated Schedule

33. February 28, 2006Critical Design Review (CDR)33 Milestone I Deliverables (3/21) FPGA –sample/store and drive all analog signals Wire wrap prototype –running boot loader & minimal system –talk to all peripherals PCB –rev 1 populated and testing Enclosure –fully specified and drafted

34. February 28, 2006Critical Design Review (CDR)34 Milestone II Deliverables (4/18) FPGA –can establish laser lock –lock monitor/recovery in alpha stage –full communication with PCB/CPU PCB –rev 2 debugged and running –ready for rev 3 if necessary Draft of user and technical manuals

35. February 28, 2006Critical Design Review (CDR)35 Expo Deliverables (5/4) System –user can lock laser manually or by computer –will detect and recover from broken lock Form factor –enclosure is ready to be installed in client lab Documentation –completed user manual and technical manual

36. February 28, 2006Critical Design Review (CDR)36 Project Responsibilities A.R. Hertneky –PCB layout, FPGA development, laser system modifications, user manual J.W. O’Brien –System-level architecture/software, chassis/UI design, test procedure design, CPLD development, technical manual J.T. Shin –Analog interfaces, FPGA on-chip peripherals, peripheral simulation, technical manual C.S. Wessels –Graphical LCD driver, FPGA development, boot loader and CPU firmware, user manual

37. February 28, 2006Critical Design Review (CDR)37 Thank you. Questions? “I don’t know; and when I know nothing, I usually hold my tongue.” – Creon in Oedipus the King