1. Enabling Technologies for Reconfigurable Computing Enabling Technologies for Reconfigurable Computing Part 3: Resources for RC Wednesday, November 21, 14.00 – 15.30 hrs. Reiner Hartenstein University of Kaiserslautern November 21, 2001, Tampere, Finland

2. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 2 Schedule timeslot 08.30 – 10.00Reconfigurable Computing (RC) 10.00 – 10.30coffee break 10.30 – 12.00Stream-based Computing for RC 12.00 – 14.00lunch break 14.00 – 15.30Resources for RC 15.30 – 16.00coffee break 16.00 – 17.30FPGAs: recent developments

3. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 3 >> Configware Industry Configware Industry Terminology MoPL data-procedural language Xputer architecture and circuitry http://www.uni-kl.de

4. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 4 Configware heading for mainstream Configware market taking off for mainstream FPGA-based designs more complex, even SoC No design productivity and quality without good configware libraries (soft IP cores) from various application areas. Growing no. of independent configware houses (soft IP core vendors) and design services AllianceCORE & Reference Design Alliance Currently the top FPGA vendors are the key innovators and meet most configware demand.

5. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 5 OS for PLDs separate EDA software market, comparable to the compiler / OS market in computers, Cadence, Mentor, Synopsys just jumped in. < 5% Xilinx / Altera income from EDA SW

6. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 6 Xilinx Alliances The Software AllianceEDA Program... Xilinx Inc.'s Foundation... free WebPACK downloadable tool palette The Xilinx XtremeDSP Initiative (with Mentor Graphics) MathWorks / Xilinx Alliance. The Wind River / Xilinx alliance #

7. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 7 The Software Alliance EDA Program provides a wide selection of EDA tools Acugen Software, Agilent EEsof EDA, Aldec, Aptix, Auspy Development, Cadence, Celoxica, Dolphin Integration, Elanix, Exemplar, Flynn Systems, Hyperlynx, IKOS Systems, Innoveda, Mentor Graphics, MiroTech, Model Technoloy, Protel International, Simucad, SynaptiCAD, Synopsys, Synplicity, Translogic, Virtual Computer Corporation. helps leading EDA vendors to integrate Xilinx Alliance software tightly into their tools

8. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 8 The Xilinx AllianceCORE program a cooperation between Xilinx and third-party core developers, to produce a broad selection of industry-standard solutions for use in Xilinx platforms. - Partners are: Amphion Semiconductor, Ltd. ARC Cores CAST, Inc. DELTATEC Derivation Systems, Inc. Dolphin Integration (Grenoble) Eureka Technology Inc. Frontier Design Inc. GV & Associates, Inc. inSilicon Corporation iCODING Technology Inc. Loarant Corporation Mindspeed Technologies - A Conexant Business (formerly Applied Telecom) | MemecCore Mentor Graphics Inventra NewLogic Technologies, Inc. (Europe) NMI Electronics Paxonet Communications, Inc. Perigee, LLC Rapid Prototypes Inc. sci-worx GmbH (Hannover, Germany) SysOnChip TILAB (Telecom Italia Lab) VAutomation Virtual IP Group, Inc. XYLON.

9. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 9 The Xilinx Reference Design Alliance Program The Xilinx Reference Design Alliance Program helps the development of multi-component reference designs that incorporate Xilinx devices and other semiconductors. The designs are fully functional, but no warranties, no liability. Partners are:. ADI Engineering Innovative Integration JK microsystems, Inc. LYR Technologies NetLogic Microsystems

10. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 10 The Xilinx University Program The Xilinx University Program provides Xilinx Student Edition Software, Professor Workshops, a Xilinx University User Group, Presentation Materials and Lab Files, Course Examples, Research, Books, etc.

11. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 11 Altera offers over a hundred IP cores (1) modulator, synchronizer, DDR SDRAM controller, Hadamar transform, interrupt controller, Real86 16 bit microprocessor, floating point, FIR filter, discrete cosine, ATM cell processor, and many others. controller, UART, microprocessor, decoder, bus control, USB controller, PCI bus interface, viterbi controller, fast Ethernet MAC receiver or transmitter, Altera offers over a hundred IP cores like, for example:

12. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 12 Altera offers over a hundred IP cores (2) from Altera | AMIRIX Systems, Inc. Amphion Semiconductor, Ltd. Arasan Chip Systems, Inc. CAST, Inc. Digital Core Design Eureka Technology Inc. HammerCores Innocor Ktech Telecommunications, Inc. Lexra Computing Engines Mentor Graphics - Inventra Modelware Ncomm, Inc. NewLogic Technologies Northwest Logic Nova Engineering, Inc. Palmchip Corporation Paxonet Communications PLD Applications Sciworx Simple Silicon Tensilica TurboConcept.

13. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 13 Altera IP core design services Altera IP core design services are available from: Northwest Logic

14. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 14 Altera Certified Design Center (CDC) Program Certified Design Center (CDC) Program: Barco Silex El Camino GmbH Excel Consultants Plextek Reflex Consulting Sci-worx Tality Zaiq Technologies.

15. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 15 The Altera Consultants Alliance Program (ACAP): The Altera Consultants Alliance Program (ACAP): lists 41 offices in North America and 29 in the rest of the world.

16. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 16 Devlopment boards Devlopment boards are offered from: Altera El Camino GmbH Gid'el Limited Nova Engineering, Inc. PLD Applications Princeton Technology Group RPA Electronics Design, LLC Tensilica.

17. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 17 Consultants and services not listed by Xilinx nor Altera (index) Algotronix, Edinburgh, Andraka Consulting Group Arkham Technology, Pasadena, CA Barco Silex, Louvain-la-Neuve, Belgium, Bottom Line Technologies, Milford, NJ Codelogic, Helderberg, South Africa, Coelacanth Engineering, Norwell, MASS Comit Systems, Inc., Santa Clara, CA EDTN Programmable Logic Design Center Flexibilis, Tampere, Finland, Geoff Bostock Designs, Wiltshire, England, Great River Technology, Alberquerque, NM, New Horizons GB Ltd, United Kingdom, North West Logic Silicon System Solutions, Canterbury, Australia, Smartech, Tampere, Finland, Tekmosv, Austin, Texas, The Rockland Group, Garden Valley, CA Nick Tredennick, Los Gatos, California, Vitesse,

18. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 18 Consultants and services not listed by Xilinx nor Altera (1) Algotronix, Edinburgh, Reconfigurable Computing and FPL in software radio, communications and computer security Andraka Consulting Group high performance FPGA designs for DSP applications Arkham Technology, Pasadena, low cost IP cores for Xilinx and Atmel, embedded processor, DSP, wireless communication, COM / CORBA / DirectX, client-server database programming, software internationalization, PCB design Barco Silex, Louvain-la-Neuve, Belgium, IP integration boards for ASIC and FPGA, consultancy, design, sub-contracting

19. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 19 Consultants and services not listed by Xilinx nor Altera (2) Bottom Line Technologies, Milford, New Jersey, FPGA design, training, designing Xilinx parts since 1985 Codelogic, Helderberg, South Africa, consulting, FPGA design services Coelacanth Engineering, Norwell, Massachusetts, design services, test development services, in wireless communication, DSP-based instrumentation, mixed-signal ATE Comit Systems, Inc., Santa Clara, California, DSP, ASIC, networking, embedded control in avionics -- FPGA / ASIC design and system software EDTN Programmable Logic Design Center

20. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 20 Consultants and services not listed by Xilinx nor Altera (3) FirstPass, Castle Rock, Colorado Vitesse, ASIC design Flexibilis, Tampere, Finland, VHDL IP cores for Xilinx products Geoff Bostock Designs, Wiltshire, England, FPGA design services Great River Technology, Alberquerque, New Mexico, FPGA design services in digital video and point-to-point data transmission for aerospace, military, and commercial broadcasters New Horizons GB Ltd, United Kingdom, FPGA design and training, Xilinx specialist North West Logic; FPGA and embedded processor design in digital communications, digital video

21. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 21 Consultants and services not listed by Xilinx nor Altera (4) Silicon System Solutions, Canterbury, Australia, VHDL IP cores for the ASIC and FPGA/CPLD/EPLD markets Smartech, Tampere, Finland, ASIC and FPGA design Tekmosv, Austin, Texas, Multiple Designs on a Single Gate Array, HDL synthesis, design conversions, chip debug, test generation The Rockland Group, Garden Valley, California, a TeleConsulting organization about logic design for FPGAs Nick Tredennick, Los Gatos, California, investor and consultant

22. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 22 >> Terminology Configware Industry Terminology MoPL data-procedural language Xputer architecture and circuitry http://www.uni-kl.de

23. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 23 Terminology

24. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 24 Terminology & Acronyms Software (SW): procedural sources* Configware (CW): structural sources Hardware (HW): hardwired platforms ASIC: customizable hardwired platforms Flexware (FW): reconfigurable platforms FPGA: field-programmable gate array FPL: field-programmable logic RC: reconfigurable computing RL: reconfigurable logic *) note: firmware is SW !

25. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 25 Stream-based Computing (2) terms: DPU: datapath unit DPA: datapath array rDPU: reconfigurable DPU rDPA: reconfigurable DPA stream-based computing: using complex pipe network (super-systolic: Kress et al.)

26. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 26 Confusing Terminology Computer Science and EE as well as ist R&D and applicatgion areas suffer from a babylonial confusion. Communication not only between Computer Science and EE, but also between ist special areas, even between ist different abstrac tion levels is made difficult – mainly because of immature terminology in relation to reconfigurable circuits and their applications. Terms are rarely standardized and often used with drastically different meanings – even within then same special area. Often terms have been so badly coined, that they are not self- explanatory, but mesleading. A demonstratory example is the comparizon of terms used used in VHDL and Verilog. Ideal are "intuitive" terms. But often Intuition yields the wrong idea. Whenever a new term appears in teaching, I often have to tell the students, that the term does not mean, what he believes.

27. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 27 Terms (1). TermMeaningExample HardwarehardwiredProcessor, ASIC FlexwareReconfigurable (structurally programmable) FPLA, FPGA, KressArray FirmwareMicroprogramme (rarely used after introduction of RISC proc.) IBM 360 Computer Family Softwareprocedural programs (sequentially executable by a CPU) Word, C, OS, Compiler, etc. Configwarestructural programs, soft IP cores, personalizing CPLD, FPGA, or other Flexware for rDPA FPGA configuration, e. g. as a logic circuit, state machine, datapath, function [à la Ingo Kreuz]

28. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 28 Terms (2). TermMeaningExample dataobjects of computing “data” property depends on the moment of watching Bits, numbers, operands, results, any text (also compiler input) lists, graphs, tables, images,... data streamordered, also parallel data word lists, obtained by scheduling I/O data streams for systolic or other arrays programmingpersonalisation by loading programm code procedural code or structural code: for (re)configuration programsource text or object code for programming procedural oder structural [à la Ingo Kreuz]

29. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 29 Terms (3). TermMeaningExample boot programsimple program to enable programming - usually saved in non-volatile memory comparable to the starter of the motor of a car bootingload and execute a boot program [à la Ingo Kreuz]

30. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 30 Hardware Terms (1) TermMeaningExample machineexecution unit, driven by deterministic sequencer von Neumann machine „dataflow machine“ not a machine, since without a deterministic sequencer (exotic concept) (sleeping research area) CPUInstruction Set Processor ("von Neumann”): program counter (instruction sequencer) and DPU - mode of operation: deterministically instruction-driven ARM, Pentium core, [à la Ingo Kreuz]

31. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 31 Hardware Terms (2) TermMeaningExample DPUdata path unit, processes operands - no CPU since without sequencer - no maschine ALU with registers, multiplexers etc. ComputerCPU with RAM and interfaces Parallel Computer ensemble of several Computers Xputerdeterministically data-driven Machine, (transport-triggered) - data counter(s) used instead of a program counterm MoM architectures (Kaiserslautern) dataflow machine indeterministically data-driven (execution sequence unpredictable) (sleeping research area) [à la Ingo Kreuz]

32. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 32 Terms on Parallelism (1) TermMeaningExample parallelismseveral levels of parallelism distinguished parallel processes, parallelism at instruction set level, pipelines, concurrentparallel processes run on different CPUs of a parallel computer - may occasionally exchange signals or data weather prognisis, complex simulations, etc. ISP (instruction set parallelism) several CPUs run in parallel by clocked synchronization VLIW (very long instruction word) computer [à la Ingo Kreuz]

33. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 33 Terms on Parallelism (2) TermMeaningExample pipeliningseveral uniform or different DPUs running simultaneously - connected to a pipeline by buffer registers. pipelined CPUs, pipe networks, systolic, etc. chainingseveral uniform or different DPUs running simultaneously - connected to a pipeline without buffer registers Schaltnetze, komplexe arithmetische Operatoren Pipe networkEnsemble of DPUs, also multiple pipelines, also with irregular or wild structures systolisc arrays, stream-based computing arrays [à la Ingo Kreuz]

34. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 34 Terms on Parallelism (3) TermMeaningExample Systolic ArrayPipe network with only linear (straight-on, no branching), uniform pipelines (all DPUs hardwired and with same functionality) pipelines Matrix computation, DSP, DNA sequencing, etc. stream-based computing arrays (super-systolic arrays) pipe network, configured before fabrication image processing, DSP, complex functions and algorithms (coarse grain) reconf. stream- based arrays stream-based arrays, configurable after fabrication KressArray [à la Ingo Kreuz]

35. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 35 Counterparts categorypropertycounterpart programing mode procedural (classical) structural (synthesis, design) - „field-programmable“, PLA „programming“, etc. machine: principle of operation controlflow-driven (instruction-driven) : v. Neumann Data-driven: Xputer machine system: principle of operation instruction-flow-driven (parallel computer etc.) Data-stream-based (systolisc array, DPU array, KressArray) Set-up time (datapaths switched thru) during run time; (instruction-driven) before run time: FPGA (at compile time) Gate Array (at fabrication) [à la Ingo Kreuz]

36. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 36 >> MoPL data-procedural language Configware Industry Terminology MoPL data-procedural language Xputer architecture and circuitry http://www.uni-kl.de

37. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 37 Fundamental Ideas available (1) Data Sequencer Methodology Data-procedural Languages (Duality w. v. N.)... supporting memory bandwidth optimization Soft Data Path Synthesis Algorithms Parallelizing Loop Transformation Methods Compilers supporting Soft Machines SW / CW Partitioning Co-Compilers

38. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 38 Fundamental Ideas available (2) Programming Xputers Similarities to programming computers How not to get confused by similarities What benefits vs. Computers ?

39. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 39 Programming Language Paradigms easy to learn

40. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 40 Similar Programming Language Paradigms very easy to learn

41. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 41 JPEG zigzag scan pattern x y EastScan is step by [1,0] end EastScan; SouthScan is step by [0,1] endSouthScan; -> Declarations NorthEastScan is loop 8 times until [*,1] step by [1,-1] endloop end NorthEastScan; SouthWestScan is loop 8 times until [1,*] step by [-1,1] endloop end SouthWestScan; HalfZigZag is EastScan loop 3 times SouthWestScan SouthScan NorthEastScan EastScan endloop end HalfZigZag; goto PixMap[1,1] HalfZigZag; SouthWestScan uturn (HalfZigZag) HalfZigZag data counter 1 3 2 4

42. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 42 >> Xputer architecture and circuitry Configware Industry Terminology MoPL data-procedural language Xputer architecture and circuitry http://www.uni-kl.de

43. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 43 GAG = Address Generator Generic GAG Scheme Limit Stepper Base Stepper GAG Address Stepper B0B0 AA L0L0 A  A L B 0 [] | || | limit

44. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 44 GAG: Address Stepper GAG = Address Generator Generic + / – Escape Clause End Detect Step Counter =o LA  A init tag A Address endExec maxStepCount 0 B Limit BasestepVector []| |  A L B 0 [] | || | limit GAG: Address Stepper

45. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 45 Generic Sequence Examples Limit Slider Base Slider GAG Address Stepper B0B0 AA L0L0 A

46. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 46 floor F address Slider Operation Demo Example B 0

47. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 47 MoM Xputer Architecture rDPA Multiple RAM banks Smart memory interface Scan Window „Cache“

48. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 48 MoM Architecture Features Scan Cache Size adjustable at run time Any other shape than square supported 2-dimensional memory space Supports generic „scan patterns“ –Subject of parallel access transformations –compare Francky Cathoor et al. Supports visualization

49. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 49 Herz‘ MoM Xputer Architecture Multiple RAM banks KressArray smart memory interface Scan Window „Cache“

50. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 50 MoM Application Examples Image Processing Grid-based design rule check [1983 * ] –4 by 4 word scan cache –Pattern-matching based –Our own nMOS „DPLA“ design –design rule violation pixel map automatically generated from textual design rules –256 M&C nMOS, 800 single metal CMOS –Speed-up > 10000 vs. Motorola 68000 *) „machine“ not yet discovered

51. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 51 Schedule timeslot 08.30 – 10.00Reconfigurable Computing (RC) 10.00 – 10.30coffee break 10.30 – 12.00Stream-based Computingfor RC 12.00 – 14.00lunch break 14.00 – 15.30Resources for RC 15.30 – 16.00coffee break 16.00 – 17.30FPGAs: recent developments

52. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 52 >>> Coarse Grain - END -