1. Reconfigurable Computing S. Reda, Brown University Reconfigurable Computing (EN2911X, Fall07) Lecture 17: Application-Driven Hardware Acceleration (3/4) Prof. Sherief Reda Division of Engineering, Brown University http://ic.engin.brown.edu

2. Reconfigurable Computing S. Reda, Brown University Viterbi algorithm A dynamic programming algorithm for finding the most likely sequence of hidden states, the Viterbi path, that results in a sequence of observed events. Originally devised by Andrew Viterbi in 1967 as an error- correction scheme for noisy digital communication links. Widely used in decoding the convolutional codes for both CDMA and GSM digital cellular, dial-up modems, satellite, deep-space communications and 802.11 wireless LANs. Also used in speech recognition, computational linguistics, and bioinformatics.

3. Reconfigurable Computing S. Reda, Brown University Viterbi decoders in digital communication systems

4. Reconfigurable Computing S. Reda, Brown University 1. Encoding using convolution codes Each input bit is coded onto 2 output bits. The 2 outputs bits are produced by using modulo-2 adders. The selection of which bits are to be added to produce an output bit is called the generating polynomial O 1 = (u 0 +u 1 +u -1 +u -2 )mod 2 O 2 = (u 1 +u 0 +u -2 ) mod 2 + + O1O1 O2O2 u1u1 u0u0 u -1 u -2

5. Reconfigurable Computing S. Reda, Brown University Example Assume the input sequence is 1011 What is the output? 11 11 01 11 01 01 11 Example by C. Langton

6. Reconfigurable Computing S. Reda, Brown University Truth table presentation

7. Reconfigurable Computing S. Reda, Brown University State transition graph representation O 1 O 2 =00 de Bruijn graph. Not all outputs are shown O 1 O 2 =00O 1 O 2 =11 O 1 O 2 =00 O 1 O 2 =01 O 1 O 2 =10

8. Reconfigurable Computing S. Reda, Brown University Tree representation

9. Reconfigurable Computing S. Reda, Brown University Trellis diagram Not all transitions are shown

10. Reconfigurable Computing S. Reda, Brown University Output of the encoder for various inputs How can we devise a good generating polynomial? Let’s say we receive 01 11 01 11 01 01 11. It is not one of the possible 16 sequences. How do we decode it? inputEncoder output 0000 00 00 00 00 00 00 00 0001 00 00 00 11 11 10 11 0010 00 00 11 11 10 11 00 0011 00 00 11 00 01 01 11 0100 00 11 11 10 11 00 00 0101 00 11 11 01 00 10 11 0110 00 11 00 01 01 11 00 0111 00 11 00 10 10 01 11 1000 11 11 10 11 00 00 00 1001 11 11 10 00 11 10 11 1010 11 11 01 00 10 11 00 1011 11 11 01 11 01 01 11 1100 11 00 01 01 11 00 00 1101 11 00 01 10 00 10 11 1110 11 00 10 10 01 11 00 1111 11 00 10 01 10 01 11

11. Reconfigurable Computing S. Reda, Brown University 2. Decoding received sequences using the Viterbi algorithm Let’s decode the received sequence 01 11 01 11 01 01 11 000 001 010 011 100 101 110 111 0111011101 11 cost 00 11 1 1

12. Reconfigurable Computing S. Reda, Brown University 2 nd step Let’s decode the received sequence 01 11 01 11 01 01 11 000 001 010 011 100 101 110 111 0111011101 11 cost 00 11 3 1 00 11 00 1 3

13. Reconfigurable Computing S. Reda, Brown University 3 rd step Let’s decode the received sequence 01 11 01 11 01 01 11 000 001 010 011 100 101 110 111 0111011101 11 cost 00 11 4 4 00 11 00 2 2 10 5 1 3 01 11 00 01 10 11 00 3

14. Reconfigurable Computing S. Reda, Brown University 4 th step Let’s decode the received sequence 01 11 01 11 01 01 11 A any step, there is only one path from the initial state to any state. In case more than one path converge to a node, always pick the minimum 000 001 010 011 100 101 110 111 0111011101 11 cost 00 11 min(3, 6) 4 11 00 11 00 3 1 10 3 3 4 01 11 00 01 10 11 00 3 11 10 11 00 01 10

15. Reconfigurable Computing S. Reda, Brown University 5 th step Let’s decode the received sequence 01 11 01 11 01 01 11 000 001 010 011 100 101 110 111 0111011101 11 cost 00 11 4 4 00 11 00 5 4 10 3 3 1 01 11 00 01 10 11 00 4 11 10 11 00 01 10 01 11 01 11 01 11

16. Reconfigurable Computing S. Reda, Brown University 6 th step Let’s decode the received sequence 01 11 01 11 01 01 11 000 001 010 011 100 101 110 111 0111011101 11 cost 00 11 00 11 00 10 01 11 00 01 10 11 00 11 10 11 00 01 10 01 1 4 4 4 4 3 5 3 11 01 11 01 11

17. Reconfigurable Computing S. Reda, Brown University Finally Winner path is 000, 100, 010, 101, 110, 011, 001, 000 with input sequence 1011000 What is runtime using SW on a general-purpose CPU? What is the runtime using an FPGA? 000 001 010 011 100 101 110 111 0111011101 11 cost 00 11 00 11 00 10 01 11 00 01 10 11 00 11 10 11 00 01 10 11 1 5 6 6 3 5 3 4 01 11 01 11 01 11

18. Reconfigurable Computing S. Reda, Brown University Summary So far we have covered popular application-driven algorithms to accelerate in FPGAs –FFT for signal and image processor as an example of divide and conquer algorithms –Speech recognition applications –Viterbi algorithm for digital communication as an example of dynamic programming algorithms Next time, we cover some popular algorithms for bioinformatics

19. Reconfigurable Computing S. Reda, Brown University Project updates 2 nd project report extended until Sunday Dec 2 nd. Make sure to add the new material to the content of the 1 st report. The new report is worth 10 points. Main evaluation criterion is your progress on the project plan you outlined in the first report. –How thorough and creative your ideas develop? –How meticulous is the experimental setup? –How do the carried out experiments serve towards the project goals? Make sure to also send me a couple of slides by Monday Dec 3rd to present on Tuesday Dec 4 th (last lecture)