1. A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning Roman Lysecky, Frank Vahid* Department of Computer Science and Engineering University of California, Riverside {rlysecky, vahid}@cs.ucr.edu *Also with the Center for Embedded Computer Systems at UC Irvine This work was supported in part by the National Science Foundation and the Semiconductor Research Corporation

2. R. Lysecky2/11 Introduction Warp Processors – Dynamic HW/SW Partitioning µPµP I$ D$ FPGA Profiler Dynamic Part. Module (DPM) Profile application to determine critical regions2 Profiler Initially execute application in software only1 µPµP I$ D$ Partition critical regions to hardware 3 Dynamic Part. Module (DPM) Program configurable logic & update software binary 4 FPGA Partitioned application executes faster with lower energy consumption 5 Study the benefits of warp processing for FPGA soft processor cores

3. R. Lysecky3/11 Introduction Warp Processors – Dynamic HW/SW Partitioning Dynamic HW/SW Partitioning Enabler – Synthesis from Binaries [Stitt & Vahid, 2005][Stitt & Vahid, 2002] Advantages Does not require any special compilers Completely transparent Provides separation of function and architecture Avoid complexities of supporting different FPGAs Opens additional market segments (i.e., all software developers) that otherwise would not use FPGAs and CAD Binary SW Profiling Standard Compiler Binary Profiling CAD Tools Traditional partitioning done here FPGAProc. FPGAProc. FPGAProc. Profiling CAD Tools FPGAProc. Profiling CAD Tools Dynamic Hardware/Software Partitioning: A First Approach, DAC’03 A Configurable Logic Fabric for Dynamic Hardware/Software Partitioning, DATE’04 Dynamic FPGA Routing for Just-in-Time FPGA Compilation, DAC’04

4. R. Lysecky4/11 Introduction Soft Processor Cores FPGA vendor currently providing soft processor cores Xilinx – PicoBlaze and MicroBlaze Altera – NIOS and NIOS II Advantages Configurability Add custom instructions/coprocessors Configurable instruction/data caches Quickly integrate processor within any FPGA Easy to build multi-processor systems Disadvantages Higher power consumption and decreased performance Compared to hard-core embedded processor Proc. FPGA * << Proc. * I$D$ How can warp processing benefit soft processor cores?

5. R. Lysecky5/11 Introduction MicroBlaze Soft Processor Core MicroBlaze Soft Processor Core 32-bit configurable processor core with three-state pipeline Execution frequency as high as 150 MHz 85 MHz using Spartan3 FPGA Configurable instruction and data caches Configurable HW datapath components Multiplier to support mul instruction Divider to support idiv instruction Barrel shifter to support bs and bsi instructions FPGA Micro Blaze Periph1 d_lmb i_lmb opb lmb_cntrl Instr. BRAM Data BRAM lmb_cntrl Periph2

6. R. Lysecky6/11 MicroBlaze Warp Processor Single Processor System Micro Blaze Periph1 d_lmb i_lmb opb lmb_cntrl Instr. BRAM FPGA Data BRAM Profiler lmb_cntrl Periph2 BRAM Interface Dynamic Part. Module (DPM) WCLA Binary Decompilation Binary HW Bitstream RT Synthesis Partitioning Binary Updater Binary Updated Binary Binary Std. HW Binary JIT FPGA Compilation A Configurable Logic Fabric for Dynamic Hardware/Software Partitioning, DATE’04 Dynamic FPGA Routing for Just-in-Time FPGA Compilation, DAC’04

7. R. Lysecky7/11 MicroBlaze Warp Processor Multi-Processor System FPGA Micro Blaze Instr. BRAM Data BRAM Micro Blaze Instr. BRAM Data BRAM Micro Blaze Instr. BRAM Data BRAM Dynamic Part. Module (DPM) A Configurable Logic Fabric for Dynamic Hardware/Software Partitioning, DATE’04 Dynamic FPGA Routing for Just-in-Time FPGA Compilation, DAC’04

8. R. Lysecky8/11 Micro Blaze P1 opb Instr. BRAM FPGA Data BRAM Profiler BRAM Intrf. DPM WCLA P2 MicroBlaze Warp Processor Warp Configurable Logic Architecture (WCLA) Warp Configurable Logic Architecture (WCLA) Data address generators (DADG) and Loop control hardware (LCH) Provides fast, efficient coprocessor interface Fast, single-cycle 32-bit multiplier-accumulator (MAC) Ideally, WCLA would use existing FPGA for configurable logic JIT FPGA compilation tools currently only support our custom CAD-oriented FPGA DADG & LCH Existing FPGA (250 MHz) Reg0 32-bit MAC Reg1 Reg2 Custom FPGA (250 MHz) A Configurable Logic Fabric for Dynamic Hardware/Software Partitioning, DATE’04 Dynamic FPGA Routing for Just-in-Time FPGA Compilation, DAC’04

9. R. Lysecky9/11 MicroBlaze Warp Processor Performance Speedup (Single Critical Kernel) Average speedup of 5.8X using warp processing MicroBlaze warp processor is on average 1.3X faster than 325MHz ARM10

10. R. Lysecky10/11 MicroBlaze Warp Processor Energy Consumption (Single Critical Kernel) Average energy reduction of 57% using warp processing MicroBlaze warp processor requires on average 26% less energy than 325MHz ARM10

11. R. Lysecky11/11 MicroBlaze Warp Processor Conclusions & Future Work Conclusions Studied the benefits of warp processing for FPGA soft processor cores (MicroBlaze) Average speedups of 5.8X (>10X possible for some applications) Average energy reduction of 58% Demonstrated MicroBlaze warp processor is competitive with hard- core embedded processors Speedup of 1.3X compared to 325MHz ARM10 Energy reduction of 26% compared to 325MHz ARM10 Future Work Prototyping our custom FPGA and warp processors Supporting a wider range of applications (PDA/desktop/server) Incorporating advances on-chip configurable structures