1. UWB Amplifier Sarah Kief and Saif Anwar Advisor: Dr. Prasad Shastry 2008 Senior Project Bradley University Electrical Engineering

2. Outline Where we left off Where we left off Distributed Amplifier Design Distributed Amplifier Design Microstrip Line Design Microstrip Line Design Coplanar Wave Guide Design Coplanar Wave Guide Design M-derive Design M-derive Design Near future activities Near future activities

3. Where we left off Picked transistor - NE4210S01 Picked transistor - NE4210S01 Cutoff max at 20 GHz Cutoff max at 20 GHz Designed lumped element components Designed lumped element components Design Equations Design Equations

4. Design Equations

5. Where we left off Picked transistor - NE4210S01 Picked transistor - NE4210S01 Cutoff max at 20 GHz Cutoff max at 20 GHz Designed lumped element components Designed lumped element components Chose biasing parameters from the DC-IV curves Chose biasing parameters from the DC-IV curves Vds=1[V], Vgs=-.45[V] Vds=1[V], Vgs=-.45[V]

6. Bias Point Selection Vds of 2 volts and Ids of 10mA for noise figure.

7. Where we left off Picked transistor - NE4210S01 Picked transistor - NE4210S01 Cutoff max at 20 GHz Cutoff max at 20 GHz Designed lumped element components Designed lumped element components Chose biasing parameters from the DC-IV curves Chose biasing parameters from the DC-IV curves Vds=1[V], Vgs=-.45[V] Vds=1[V], Vgs=-.45[V] Built / simulated lumped element model with 1 transistor Built / simulated lumped element model with 1 transistor 7 dB 7 dB

8. Distributed Amplifier Design Lumped element model built in ADS Lumped element model built in ADS 2 and 3 transistor designs 2 and 3 transistor designs Simulations Simulations Gain flatness Gain flatness Phase linearity Phase linearity Stability Stability

9. 3 Transistor M-derived Lumped Element Network

10. Simulations

11. Simulations

12. Microstrip Line Design Translated lumped element components into respective lengths and widths in the MSTRIP program Translated lumped element components into respective lengths and widths in the MSTRIP program Capacitors Zo=30 ohms Capacitors Zo=30 ohms Inductor Zo=90 ohms Inductor Zo=90 ohms Built layout in ADS and simulated Built layout in ADS and simulated Compared microstrip simulation results to lumped element simulations Compared microstrip simulation results to lumped element simulations

13. Component Values Capacitors (pF) width(mm) length (mm) Inductors (nH) width(mm) length (mm) 9.54E-142.670220.53356.34E-100.7035561.3820 1.50E-132.670220.83617.90E-100.7035561.7234 2.40E-092.6702213422.24004.24E-100.7035560.9249 2.20E-060.7035564799.2267 5.63E-110.7035560.1228 Lambda EFF (mm) 15.535 16.361 1.941875 2.045125 Frequency 1.20E+10 Zo (ohms) 30 90 Cap = f * lambda eff * cap * zo L = f * lambda eff * in/zo

14. Microstrip Layout

15. Simulations 45678910311 -100 0 100 -200 200 freq, GHz phase(S(2,1))

16. Simulations

17. Coplanar Wave Guide Design Chose RT/Duriod 6002 board Chose RT/Duriod 6002 board Thickness : 20 mils,.508 mm Thickness : 20 mils,.508 mm Dielectric Constant : 2.94 Dielectric Constant : 2.94 1 oz copper plating 1 oz copper plating High mechanical strength High mechanical strength

18. Coplanar Wave Guide Design Design wave guide to test transistors Design wave guide to test transistors Layout Layout Designed width and length of the layout using Line calc Designed width and length of the layout using Line calc Dimensions Dimensions Width = 1.017 mm Width = 1.017 mm Air Gap =.808 mm Air Gap =.808 mm Length = 10 mm Length = 10 mm Constructed layout in ADS Constructed layout in ADS Tested and simulated in ADS Tested and simulated in ADS

19. NE4210S01 Transistor Pad Layout

20. Full Coplanar Wave Guide

21. Half Coplanar Wave Guide Layout

22. ADS Schematic of Coplanar Waveguide

23. Layout Simulation

24. LmLm CmCm Constant-k LPFM-Derived LPF Need for M-Derived Filter Design To avoid padding capacitor. Useful in the layout design. Easier for optimization purpose. M-Derive Design Layout

25. L m = L*(k-m 2 )/4*m k = m*Cg or Cd / C m where C m = Cin or Cout Cin=.33 pF, Cout=.1686 pF Lmd = 1.42 nH (for drain side) Lmg = 0.004nH (for gate side) M-Derive Equations

26. M-Derived Microstrip Layout

27. Updated Schedule Week ofTasks to complete January 25thDesigning the microstrip version of lumped element model. February 7thBoard, microstrip simulations and designing February 14 th M-derived simulations, coplanar wave guide design February 21 st Coplanar wave guide design simulation February 28 th Coplanar wave guide optimization and finalizing March 6 th Transistor optimization, coplanar wave guide finalizing March 13 th Transistor optimization, coplanar wave guide fabrication March 20 th Spring break, coplanar wave guide fabrication March 27 th Testing of transistor using coplanar wave guide April 3 rd Testing of transistor using coplanar wave guide, de-embedding April 10 th Amplifier fabrication April 17 th Amplifier fabrication April 24 th Testing amplifier May 1 st Testing amplifier May 8 th presentations

28. Near future Activities Do De-embedding to find S-Parameters on Coplanar Waveguide Do De-embedding to find S-Parameters on Coplanar Waveguide Determine the optimal number of transistors Determine the optimal number of transistors Order RT/Duriod Board Order RT/Duriod Board Test the S-Parameters of the Transistors Test the S-Parameters of the Transistors Optimize the final layout Optimize the final layout Fabricate and test the circuit Fabricate and test the circuit