1. Space vs. Speed: Binary Adders 11.3 Space vs. Speed

2. Binary Adders VHDL Adder Carry Lookahead Adder

3. 4-Bit Adder C 1 1 1 0 A 0 1 0 1 B 0 1 1 1 S 1 1 0 0

4. Adder in VHDL entity adder is port ( a: in STD_LOGIC_VECTOR (3 downto 0); b: in STD_LOGIC_VECTOR (3 downto 0); sum: out STD_LOGIC_VECTOR (3 downto 0); carry: out STD_LOGIC ); end adder;

5. std_logic_arith.vhd

7. CiCi AiBiAiBi 00011110 0 1 1 111 C i+1 C i+1 = A i & B i # C i & B i # C i & A i

9. std_logic_unsigned.vhd

11. adder.vhd

12. Binary Multiplier Half Adders are Sufficient Since there is no Carry-in in addition to the two inputs to sum 2 bit by 2 bit

13. Binary Multiplier 4 bit by 3 bit yields 7 bit result

14. Binary Adders VHLD Adder Carry Lookahead Adder

15. C 2 = G 1 + P 1 (G 0 + P 0 C 0 ) = G 1 + P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 + P 2 (G 1 + P 1 (G 0 + P 0 C 0 )) = G 2 + P 2 (G 1 + P 1 G 0 + P 0 C 0 ) = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P l P 0 C 0 G 0-3 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P l G 0 P 0-3 = P 3 P 2 P l P 0

16. Ripple Carry Adder (4-bit)

17. Typically, longest delay path through n-bit ripple carry adder is 2n + 2 Tends to be one of the largest delays in a typical computer design Counts as 2 gate delays 2 1 2 4 1 3 4 0 0 0

18. 4 4 0 0 2 4 5 6 6

19. 4 4 0 0 2 6 7 8 8 6 6

20. 4 4 0 0 2 8 9 10 6 8 6 8

21. 4 4 6 8 6 8 10 Gate Delays 16-bit Adder -- 34 Gate Delays 64-bit Adder -- 130 Gate Delays

22. Carry Lookahead Adder Uses Propogate and Generate signals to “lookahead” for incoming carry signals More complicated hardware configuration Substantial decrease in gate delays

23. PFA: Partial Full Adders Ripple Carry Carry Lookahead

24. Propagate P = A xor B If P = ‘1’ then the carry is “propagated” through. If P = ‘0’ then the carry is not “propagated” through. Generate G = A and B If G = ‘1’ a carry is “generated” regardless of the carry bit.

25. C in A B 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 C out S 0 000101100110101100010110011010111 PGPG0 001010010010100100101001001010010 For final carry determination, the Propagate signal is ANDed with the Carry Out and the Generate signal is ORed to the resulting signal. GPC in C out

26. Always Generate a Carry for A = 1, B = 0 C in A B 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 C out S 0 000101100110101100010110011010111 PGPG0 001010010010100100101001001010010 C in A B 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 C out S 0 000101100110101100010110011010111 PGPG0 001010010010100100101001001010010 Propagate the Carry in

27. C out

28. 2 4 1 2 3 4

29. 2 4 1 2 3 4 2 2 3 1 4 2 1 2 1 2 3 3 4 2 1 2 3 4 PFA For Bit # 1

30. 2 4 1 4 2 6 2 6 1 4 2 6 Bit #1 Bit #2 Bit #3 Bit #4 1 4

31. Significant Delay Reduction 4 - bit Ripple: 10 Delays CLA:6 Delays 1 CLA level: 1*4 + 2 = 6 16 - bit Ripple:34 Delays CLA: 10 Delays 2 CLA levels: 2*4 + 2 = 10 64 - bit Ripple:130 Delays CLA:14 Delays 3 CLA levels: 3*4 + 2 = 14 But at the expense of a significant increase in the number of gates used by the circuit