1. Spring 2007EE130 Lecture 35, Slide 1 Lecture #35 OUTLINE The MOS Capacitor: Final comments The MOSFET: Structure and operation Reading: Chapter 17.1

2. Spring 2007EE130 Lecture 35, Slide 2 Bias-Temperature Stress Measurement Na + located at upper SiO 2 interface  no effect on V FB Na + located at lower SiO 2 interface  reduces V FB  V FB Used to determine mobile charge density in MOS dielectric (units: C/cm 2 ) Positive oxide charge shifts the flatband voltage in the negative direction:

3. Spring 2007EE130 Lecture 35, Slide 3 Clarification: Effect of Interface Traps Traps cause “sloppy” C-V and also greatly degrade mobility in channel “Donor-like” traps are charge-neutral when filled, positively charged when empty Positive oxide charge causes C-V curve to shift toward left (more shift as V G decreases) (a) (b) (c)

4. Spring 2007EE130 Lecture 35, Slide 4 In 1935, a British patent was issued to Oskar Heil. A working MOSFET was not demonstrated until 1955. Invention of the Field-Effect Transistor

5. Spring 2007EE130 Lecture 35, Slide 5 Modern Field Effect Transistor (FET) An electric field is applied normal to the surface of the semiconductor (by applying a voltage to an overlying electrode), to modulate the conductance of the semiconductor  Modulate drift current flowing between 2 contacts (“source” and “drain”) by varying the voltage on the “gate” electrode

6. Spring 2007EE130 Lecture 35, Slide 6 The Bulk-Si MOSFET Current flowing between the SOURCE and DRAIN is controlled by the voltage on the GATE electrode Substrate Gate SourceDrain Metal-Oxide-Semiconductor Field-Effect Transistor: GATE LENGTH, L g OXIDE THICKNESS, T ox JUNCTION DEPTH, X j M. Bohr, Intel Developer Forum, September 2004 Desired characteristics: High ON current Low OFF current “N-channel” & “P-channel” MOSFETs operate in a complementary manner “CMOS” = Complementary MOS |GATE VOLTAGE| CURRENT VTVT

7. Spring 2007EE130 Lecture 35, Slide 7 N-channel vs. P-channel For current to flow, V GS > V T Enhancement mode: V T > 0 Depletion mode: V T < 0 –Transistor is ON when V G =0V P-type Si N+ poly-Si n-type Si P+ poly-Si NMOSPMOS N+ P+ For current to flow, V GS < V T Enhancement mode: V T < 0 Depletion mode: V T > 0 –Transistor is ON when V G =0V

8. Spring 2007EE130 Lecture 35, Slide 8 Enhancement Mode vs. Depletion Mode Enhancement ModeDepletion Mode Conduction between source and drain regions is enhanced by applying a gate voltage A gate voltage must be applied to deplete the channel region in order to turn off the transistor

9. Spring 2007EE130 Lecture 35, Slide 9 CMOS Devices and Circuits CIRCUIT SYMBOLS N-channel MOSFET P-channel MOSFET GND V DD S S D D CMOS INVERTER CIRCUIT V IN V OUT V IN 0 V DD INVERTER LOGIC SYMBOL When V G = V DD, the NMOSFET is on and the PMOSFET is off. When V G = 0, the PMOSFET is on and the NMOSFET is off.

10. Spring 2007EE130 Lecture 35, Slide 10 “Pull-Down” and “Pull-Up” Devices In CMOS logic gates, NMOSFETs are used to connect the output to GND, whereas PMOSFETs are used to connect the output to V DD. –An NMOSFET functions as a pull-down device when it is turned on (gate voltage = V DD ) –A PMOSFET functions as a pull-up device when it is turned on (gate voltage = GND) F(A 1, A 2, …, A N ) PMOSFETs only NMOSFETs only … … Pull-up network Pull-down network V DD A1A2ANA1A2AN A1A2ANA1A2AN input signals

11. Spring 2007EE130 Lecture 35, Slide 11 CMOS NAND Gate ABF 001 011 101 110 A F B AB V DD

12. Spring 2007EE130 Lecture 35, Slide 12 CMOS NOR Gate A F B A B V DD ABF 001 010 100 110

13. Spring 2007EE130 Lecture 35, Slide 13 CMOS Pass Gate A X Y A Y = X if A