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Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 ECE 425 - VLSI Circuit Design Lecture 3 - Transistors,

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Presentation on theme: "Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 ECE 425 - VLSI Circuit Design Lecture 3 - Transistors,"— Presentation transcript:

1 Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 425 - VLSI Circuit Design Lecture 3 - Transistors, Wires, & Parasitics Spring 2007

2 ECE 425 Spring 2007Lecture 3 - Transistors & Wires2 Announcements  Reading  Wolf 2.1-2.6

3 ECE 425 Spring 2007Lecture 3 - Transistors & Wires3 Where we are...  Last time:  CMOS Processing  Today:  Transistor Modes of Operation  More about Wires & Vias  Parasitics

4 ECE 425 Spring 2007Lecture 3 - Transistors & Wires4 Roadmap for the term: major topics  VLSI Overview  CMOS Processing & Fabrication  Components: Transistors, Wires, & Parasitics   Design Rules & Layout  Combinational Circuit Design & Layout  Sequential Circuit Design & Layout  Standard-Cell Design with CAD Tools & Verilog  Mixed Signal Concerns: D/A, A/D Conversion  Design Project: Complete Chip

5 ECE 425 Spring 2007Lecture 3 - Transistors & Wires5 Review - Transistor Structure

6 ECE 425 Spring 2007Lecture 3 - Transistors & Wires6 N Transistor Operation - Cutoff  V gs << V t : Transistor OFF  Majority carrier in channel (holes)  No current from source to drain Some Values for V tn : Book (0.5µm) : 0.7V AMI (1.5µm): 0.61V

7 ECE 425 Spring 2007Lecture 3 - Transistors & Wires7 N Transistor Operation - Subthreshold  0 < V gs < V t : Depletion region  Electric field repels majority carriers (holes)  Depletion region forms - no carriers in channel  No current flows (except for leakage current)

8 ECE 425 Spring 2007Lecture 3 - Transistors & Wires8 N Transistor Operation - ON  V gs > V t, V DS =0: Transistor ON  Electric field attracts minority carriers (electrons)  Inversion region forms in channel  Depletion region insulates channel from substrate  Current can now flow from drain to source!

9 ECE 425 Spring 2007Lecture 3 - Transistors & Wires9 N Transistor Operation - Linear  V gs > V t, V DS <V GS -V t : Linear (Active) mode  Combined electric fields shift channel and depletion region  Current flow dependent on V GS, V DS

10 ECE 425 Spring 2007Lecture 3 - Transistors & Wires10 N Transistor Operation - Saturation  V gs > V t, V DS >V GS -V t : Saturated mode  Channel “pinched off”  Current still flows due to electron drift  Current flow dependent on V GS

11 ECE 425 Spring 2007Lecture 3 - Transistors & Wires11 P Transistor Operation  Opposite of N-Transistor  V gs >> V t : Transistor OFF Majority carrier in channel (electrons) No current from source to drain  0 > V gs > V t : Depletion region Electric field repels majority carriers (electrons) Depletion region forms - no carriers in channel No current flows (except for leakage current)  V gs < V t, V DS =0: Transistor ON Electric field attracts minority carriers (holes) Inversion region forms in channel Depletion layer insulates channel from substrate Current can now flow from source to drain!

12 ECE 425 Spring 2007Lecture 3 - Transistors & Wires12 P Transistor Modes of Operation  V gs V GS -V T : Linear (Active) mode  Combined electric fields shift channel and depletion region  Current flow dependent on V GS, V DS  V gs < V t, V DS <V GS -V T : Saturation mode  Channel “pinched off”  Current still flows due to hole drift  Current flow dependent on V GS Some Values for V tp : Book (0.5µm) : -0.8V AMI (1.5µm): -1.02V

13 ECE 425 Spring 2007Lecture 3 - Transistors & Wires13 I-V Characteristics of MOS Transistors linearsaturation linear saturation n transistor p transistor

14 ECE 425 Spring 2007Lecture 3 - Transistors & Wires14 Ideal Transistor Equations  Cutoff Region: V gs < V t  Linear Region V ds < V gs - V t  (EQ 2-1)  Saturated Region V ds ≥ V gs - V t  (EQ 2-2)  (EQ 2-16) (Beware error in 1st printing of book! )  - Channel Length Modulation Parm.

15 ECE 425 Spring 2007Lecture 3 - Transistors & Wires15 More about Transistor Equations  More about k'  µ - effective surface mobility of carrier   - permittivity of gate insulator  t ox - thickness of gate insulator  Beta - a measure of gain  Some values for k'  AMI 1.5µm process:k' n =34.2µA/V 2 k’ p =11.4µA/V 2  AMI 0.5µm proces: k' n =56.3µA/V 2 k’ p =19.6µA/V 2  Agilent 0.5µm process:k' n =73.6µA/V 2 k’ p =24.8µA/V 2  Important: these equations are approximations k'   t ox  k W L

16 ECE 425 Spring 2007Lecture 3 - Transistors & Wires16 Threshold Voltage  Depends on gate capacitance, physical constants  When V sb =0:  (EQN 2-4)  (EQN 2-5)  (EQN 2-6)  (EQN 2-7)  (EQN 2-9)  (EQN 2-10) Permittivity of SiO 2 = 3.9  0 Oxide thickness (cm) Flatband voltage Work function difference Surface potential Adjustment - Ion Implant Charge stored in depletion region

17 ECE 425 Spring 2007Lecture 3 - Transistors & Wires17 Threshold Voltage - Body Effect  V t increases when V sb >0  (EQN 2-11)  (EQN 2-12)

18 ECE 425 Spring 2007Lecture 3 - Transistors & Wires18 Subthreshold Current  Current can flow even when transistor is “off”  (EQ 2-17) S - subthreshold slope (measured in mV/decade) q - charge of an electron k - Boltzmann’s constant T - temperature (Kelvin)

19 ECE 425 Spring 2007Lecture 3 - Transistors & Wires19 Wires & Vias  Creating wires (review):  Deposit insulator on chip (SiO 2 )  Deposit conducting material on chip  Selectively remove using photolithography  Use multiple layers so wires can cross over each other  Vias (Contacts) - Connect between layers  “cuts” etched through insulator  Metal connects between layers (with significant resistance) Wafer

20 ECE 425 Spring 2007Lecture 3 - Transistors & Wires20 Wiring Examples - Intel Processes Intel 0.25µm Process (Al) 5 Layers - Tungsten Vias Source: Intel Technical Journal 3Q98 Intel 0.13µm Process (Cu) Source: Intel Technical Journal 2Q02 k=3.6 Tungsten Plugs Tungsten Plugs (Poly/diff. only)

21 ECE 425 Spring 2007Lecture 3 - Transistors & Wires21 Wiring Example - IBM Process IBM 0.13µm SOI Process Source: Apple Computer www.apple.com

22 ECE 425 Spring 2007Lecture 3 - Transistors & Wires22 Metal Migration  High current density can cause metal molecules to move  Solution: size wires to keep current density with recommended range (book: 1.5mA / µm width)  Also a problem in vias that connect different layers

23 ECE 425 Spring 2007Lecture 3 - Transistors & Wires23 Metal Migration Example  Consider a 2-input NOR  Estimate the maximum current in the ground wire when both n-transistors are in saturation  Assume AMI 1.5µm process minimum-size transistors: W = 2.4µm L = 1.6µm k' n =34.2µA/V 2 V tn = 0.7V V DS = 3.3V V GS = 3.3V  What’s the current density be in a 2.4µm wide wire?

24 ECE 425 Spring 2007Lecture 3 - Transistors & Wires24 Solution - Metal Migration Example  First, Calculate I d in one transistor using EQ 2-2  Current in the ground connection will be 2 X I d  Current density is (2 X I d ) / 2.4µm

25 ECE 425 Spring 2007Lecture 3 - Transistors & Wires25 Parastic Elements  So far, we’ve concentrated on getting circuit elements that we want for digital design  Transistors  Wires  Parasitics - occur whether we want them or not  Capacitors  Resistors  Transistors (bipolar and FET)

26 ECE 425 Spring 2007Lecture 3 - Transistors & Wires26 Parasitic Capacitance  Transistors  Depends on area of transistor gate  Depends on physical materials, thickness of insulator  Given for a specific process as C g  Overlap capacitance also a concern sometimes

27 ECE 425 Spring 2007Lecture 3 - Transistors & Wires27 Parasitic Capacitance  Diffusion to substrate  Sidewall capacitance - capacitance from periphery  Bottomwall capacitance - capacitance to substrate  See Eqns. 2-19 thru 2-22 - note dependence on reverse- bias voltage V r  Rough estimate: ignore voltage & calculate for a specific process using C diff,bot, C diff,side

28 ECE 425 Spring 2007Lecture 3 - Transistors & Wires28 Parasitic Capacitance (cont’d)  Metal to substrate  Parallel plate capacitance is dominant  Need to account for fringing, too  Poly to substrate  Parallel plate plus fringing, like metal  Pitfall: don’t confuse poly over substrate with gate capacitance  Sample parasitic values: Table 2-4, p. 85  Also important: capacitance between conductors  Metal1-Metal1  Metal1-Metal2

29 ECE 425 Spring 2007Lecture 3 - Transistors & Wires29 Resistance  Depends on resistivity of material  (Rho)  Sheet resistance R s =  /t see Table 2-4, p. 85  Resistance R = R s * L / W  Corner approximation - count a corner as half a square Corner (1/2 Square) 1/2 Square Corner (1/2 Square) 1/2 Square Example: R = R s(poly) * 13 + 2*(1/2) + 3*(1/2) squares R = 4Ω/sq * 15.5 squares = 62Ω

30 ECE 425 Spring 2007Lecture 3 - Transistors & Wires30 Some Example Process Data  Book Table 2-4, p. 85 - 0.5µm process  AMI 1.5µm process (from www.mosis.org)  TSMC 0. 5µm process (from www.mosis.org)

31 ECE 425 Spring 2007Lecture 3 - Transistors & Wires31 Parasitics - Final Notes  These are approximate calculations  Grossly oversimplified  Advanced CAD tools (e.g. field solver) needed for accuracy  Process Variation  Parameter values are are not exact, but vary depending on manufacturing, etc. Typical process specifies a range for each parameter Must design chips to work for worst case - “process corners”

32 ECE 425 Spring 2007Lecture 3 - Transistors & Wires32 Example Problems - Parasitic Calculation poly metal1 ndiff Rmetal1=? Cmetal1=? Rpoly=? Cpoly=? Rndiff=? Cndiff=? 1 =0.25µm 30 Note: see Table 2-4, p. 85 for parameters

33 ECE 425 Spring 2007Lecture 3 - Transistors & Wires33 Example Problems - Parasitic Calculation poly metal1 ndiff 1 =0.25µm 30 Rmetal1= 30 / 3 ) * 0.08Ω/  = 0.8Ω Cmetal1= (30  * 0.25µm/  (3  * 0.25µm/  0.04fF/µm 2 + (30 + 3  30 + 3  0.25µm/  * 0.09fF/µm = 0.225fF + 1.485fF = 1.71fF Note: see Table 2-4, p. 85 for parameters

34 ECE 425 Spring 2007Lecture 3 - Transistors & Wires34 Example Problems - Parasitic Calculation poly metal1 ndiff 1 =0.25µm 30 Rndiff= (11 / 3 ) * 2Ω/  = 7.33Ω Cndiff = (11  * 0.25µm/  (3  * 0.25µm/  0.6fF/µm 2 + (11 + 3  11 + 3  0.25µm/  * 0.2fF/µm = 1.24fF + 1.4fF = 2.64fF Note: see Table 2-4, p. 85 for parameters

35 ECE 425 Spring 2007Lecture 3 - Transistors & Wires35 Example Problems - Parasitic Calculation poly metal1 ndiff 1 =0.25µm 30 Note: see Table 2-4, p. 80 for parameters Rpoly= ((3 / 2 ) + 1/2  + (8 / 2 )) * 4Ω/  = 24Ω Cpoly = ( ((3  * 0.25µm/  (2  * 0.25µm/   ((10  * 0.25µm/  (2  * 0.25µm/  0.09fF/µm 2 + (5 + 10  2 + 8  + 3  + 2  0.25µm/  * 0.04fF/µm = 0.15fF + 0.3fF = 0.45fF Corner approx. 1/2 

36 ECE 425 Spring 2007Lecture 3 - Transistors & Wires36 Example Problems - Parasitic Calculation poly metal1 ndiff 1 =0.25µm 30 Rmetal1=0.8Ω Cmetal1= 1.71fF Rndiff=7.33Ω Cndiff= 2.64fF Rpoly=24Ω Cpoly= 0.45fF

37 ECE 425 Spring 2007Lecture 3 - Transistors & Wires37 Example Problems - Parasitic Calculation A 1 =0.25µm What are the parasitic capacitances visible from point “A”?

38 ECE 425 Spring 2007Lecture 3 - Transistors & Wires38 Example Problems - Parasitic Calculation A 1 =0.25µm What are the parasitic capacitances visible from point “A”? Cpoly = (6  * 0.25µm/  (2  * 0.25µm/  0.09fF/µm 2 + (6 + 2  6 + 2  0.25µm/  * 0.04fF/µm = 0.675fF + 0.16fF = 0.84fF

39 ECE 425 Spring 2007Lecture 3 - Transistors & Wires39 Example Problems - Parasitic Calculation A 1 =0.25µm What are the parasitic capacitances visible from point “A”? Cgate = (3  * 0.25µm/  (2  * 0.25µm/  0.9fF/µm 2 = 0.34fF Remember: use C g, not C poly for transistor gates!

40 ECE 425 Spring 2007Lecture 3 - Transistors & Wires40 Example Problems - Parasitic Calculation A 1 =0.25µm What are the parasitic capacitances visible from point “A”? C overhang = (2  * 0.25µm/  (2  * 0.25µm/  0.09fF/µm 2 + (2 + 2  2 + 2  0.25µm/  * 0.04fF/µm = 0.0225fF + 0.08fF = 0.1fF

41 ECE 425 Spring 2007Lecture 3 - Transistors & Wires41 A 1 =0.25µm What are the parasitic capacitances visible from point “A”? Example Problems - Parasitic Calculation

42 ECE 425 Spring 2007Lecture 3 - Transistors & Wires42 Parasitic Transistors  Parasitic bipolar transistors form at N/P junctions  Latchup - when parasitic transistors turn on  Preventing latchup:  Add substrate contacts (“tub ties”) to reduce R s, R w (more about this later) OR  Use Silicon-on-Insulator

43 ECE 425 Spring 2007Lecture 3 - Transistors & Wires43 Controlling Latchup - Substrate Contacts  Purpose: connect well/substrate to power supply  Alternative term: tub tie (used by book)  Recommendations (source: Weste & Eshraghian)  Conservative: 1 substrate contact for every supply connection  Less conservative: 1 substrate contact for every 5-10 transistors  High-current circuits: use guard rings Substrate Contact Substrate Contact

44 ECE 425 Spring 2007Lecture 3 - Transistors & Wires44 Roadmap for the term: major topics  VLSI Overview  CMOS Processing & Fabrication  Components: Transistors, Wires, & Parasitics  Design Rules & Layout  Combinational Circuit Design & Layout  Sequential Circuit Design & Layout  Standard-Cell Design with CAD Tools  Systems Design using Verilog HDL  Design Project: Complete Chip

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