1. TH EDA NTHU-CS VLSI/CAD LAB 1 A Probabilistic Approach to Logic Equivalence Checking Chun-Yao Wang ( 王俊堯 ) Dept. CS NTHU 2006. 01. 06

2. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 2 Outline Introduction Previous Work Probabilistic Logic Equivalence Checking –Exact Approach –Approximate Approach Experimental Results Conclusions

3. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 3 Motivation Logic equivalence checking –Logic optimization, scan insertion, manual modification Exhaustively simulation is infeasible for practical designs

4. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 4 Problem Formulation Given two netlists N_ori, N_opt –N_ori is the original netlist –N_opt is the netlist after area/timing optimization (restructuring) The problem is to formally verify the equivalence of N_ori and N_opt

5. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 5 Outline Introduction Previous Work Probabilistic Logic Equivalence Checking –Exact Approach –Approximation Approach Experimental Results Conclusions

6. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 6 Previous Work (1/3) Probabilistic based approach –Assume circuits only consist of AND/OR/NOT gates –Probability formulae (independent signals) Symbol represents the probability of signal one a  b a b a 1 - a b a 1 - (1 - a)  (1 - b) = a + b - a  b

7. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 7 Previous Work (2/3) Assign the probability symbol to PIs Derive probability expressions Perform exponent suppression ( x m → x ) on reconvergent gates Compare the output probabilities (unique) Problem: Representation complexity a b c 1-b a × (1-b) b × c a × (1-b) + b × c – a × (1-b) × b × c = a × (1-b) + b × c – a × (b-b 2 ) × c = a × (1-b) + b × c – a × (b-b) × c = a × (1-b) + b × c E. J. McCluskey et al, "Probabilistic treatment of general combinational networks," IEEE Trans. Computer, June 1975

8. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 8 Previous Work (3/3) Assign real numbers as input probabilities instead of symbols –Evaluate output probability (number) of circuits Arithmetic operationsArithmetic operations –Problems: Aliasing occurrenceAliasing occurrence Signal correlationSignal correlation J. A. Abraham et al, " Probabilistic design verification," ICCAD, 1991

9. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 9 Aliasing Problem Two different circuits have the same output probabilityTwo different circuits have the same output probability Example:Example: –N 1 ≡N 2, but with the same output probability Multiple runs increase the confidence levelMultiple runs increase the confidence level N1N1 N2N2

10. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 10 Signal Correlation Problem Numbers cannot be assigned immediatelyNumbers cannot be assigned immediately –Numbers should be assigned after exponent suppression Example:Example: –Two inputs of G2 are correlated with signal B –Without considering exponent suppression –Considering exponent suppression ( ○ ) ( × ) G1 G2 A B

11. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 11 Outline Introduction Previous Work Probabilistic Logic Equivalence Checking –Exact Approach Aliasing-Free Probability Assignments Encoding Scheme and Alternative Operations Dealing with Signal Correlation Internal Tree-Structure Replacement –Approximate Approach Experimental Results Conclusions

12. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 12 Aliasing-Free Probability Assignments An aliasing-free assignment –x i = –a i+1 =(a i -1) 2 +1, a 1 >=3 &  Z +, i=1~n-1 –Problem: The assignments grow exponentially n <= 24 is feasible Examples: –x 1 =, x 2 =, x 3 =, …, x 6 =, … " " Teslenko, M., Dubrova, E., and Tenhunen H., "Computing a perfect input assignment for probabilistic verification", EMT'2005, May 12-15

13. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 13 Why Aliasing-Free A 3-input function has distinct functions x 1 x 2, x 3 –Assume x 1 =, x 2 =, x 3 = –The probability of each function is distributed from ~ X 1 X 2 X3X3 0 1 00 11 0 1

14. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 14 Encoding Scheme a i a iDenominators are either a i or the product of a i –,, a iSuppose the weight of bit-i is a i –Multiplication replaces addition –Reduce memory usage Examples:Examples: –x 1 = = = –x 2 = = = –x 3 = = = –x 1 × x 2 × x 3 = × × = ( )

15. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 15 Example – AND Gate Original formulation Bitwise-AND (∩) operation ( ) = ( ) ( ) = ( )

16. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 16 Shift-Add Operation When transforming two input probabilities to their equivalent probabilities –Denominators are either 3, 5, 17, …, –Shift-add operations are used to obtain the numerator instead of multiplication operations Example: – –Numerator 5 = 1 × 5 can be obtained by ( 0001 << 2 ) + 0001 = 0101 = 5 ( ) = ( )

17. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 17 Example – OR Gate Original formulation Bitwise-OR ( ∪ ) operation ( ) = ( ) ( ) = ( )

18. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 18 Dealing with Signal Correlation When transforming two input probabilities to their equivalent probabilities –The lowest common multiple suppresses the correlation of two input probabilities if the denominators have the same factor G1 G3 ( ) = ( ) ( ) =( ) G2 A B C

19. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 19 Internal Tree-Structure Replacement Example: –Verify if N 1 ≡ N 2 –Only two input assignments and are used G1 G2 B C A C N1N1 N2N2 G1 B A G2 ≡

20. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 20 Outline Introduction Previous Work Probabilistic Logic Equivalence Checking –Exact Approach Aliasing-Free Probability Assignments Encoding Scheme and Alternative Operations Dealing with Signal Correlation Internal Tree-Structure Replacement –Approximate Approach Experimental Results Conclusions

21. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 21 Approximation Structure Connect Random Probability Generator (RPG) to DUV Aliasing-free assignments are assigned to RPG’s PIs RPG produces every possible function |PO| in RPG = |PI| in DUV Verify the equivalence of S1 and S2 Verify the equivalence of L1 and L 2 RPGRPG ︰ aliasing-free assignments : S1 RPGRPG ︰ aliasing-free assignments ︰ S2 L1 L2

22. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 22 Problem Formulation Given two large netlists S1, S2 (# of required input assignments > 24) The problem is to verify the equivalence of S1 and S2 with aliasing rate (ε) ε  pr(S1  S2 ∩ L1  L2)

23. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 23 Analysis (1/3) Assume r (resource) input assignments are available, and S1, S2 (DUVs) have n PIs. What is the aliasing rate ε in using Approximation Structure to verify the equivalence of S1 and S2 ? RPGRPG ︰ aliasing-free Assignments : S1 RPGRPG ︰ aliasing-free assignments ︰ S2 L1 L2 r n r n

24. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 24 Analysis (2/3) r=2, n=3, connect 2/15, 7/15, 9/15 to the inputs of S1 Uniformly hash 16 S-functions to one L-function ε  L_0S_0~S_15 L_1S_16~S_31 L_2S_32~S_47 L_3S_48~S_63 L_4S_64~S_79 L_5S_80~S_95 L_6S_96~S_111 L_7S_112~S_127 L_8S_128~S_143 L_9S_144~S_159 L_10S_160~S_175 L_11S_176~S_191 L_12S_192~S_207 L_13S_208~S_223 L_14S_224~S_239 L_15S_240~S_255 1/3 1/5 RPGRPG S1 L1 2/15 7/15 9/15

25. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 25 ε  pr(S1 ≠ S2 ∩ L1 = L2) = pr(L1 = L2) - pr(S1 = S2) = - Assume n>24 ( ), εis simply related to r –r=8, ε  10 -77 –r=9, ε  10 -154 –r=10, ε  10 -308 –r=11, ε  10 -616 –r=12, ε  10 -1233 Analysis (3/3) L1=L2 S1=S2

26. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 26 Outline Introduction Previous Work Probabilistic Logic Equivalence Checking –Exact Approach –Approximate Approach Experimental Results Conclusions

27. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 27 Experimental Results – exact approach Circuits|PI||PO|Max a i / Max TFI |PI| Tree (Y/N) Time (s) Ours / BDD Mem. (MB) Ours / BDD i9886313 / 13N0.76 / 0.666.66 / 6.45 x4947115 / 15Y0.22 / 0.225.48 / 5.57 i313267 / 32Y0.05 / 0.053.41 / 4.80 i51336619 / 19Y0.17 / 0.235.62 / 5.30 i81338117 / 17Y1.71 / 1.4411.00 / 10.00 apex61359922 / 24Y0.51 / 0.429.50 / 6.23 x31359923 / 24Y1.41 / 0.4515.00 / 6.52 i6138675 / 5N0.21 / 0.325.87 / 5.94 frg214313923 / 25Y2.35 / 0.8715.00 / 7.63 i7199676 / 6N0.25 / 0.466.25 / 6.33 des25624518 / 19Y5.23 / 4.4215.00 / 15.00

28. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 28, ε  10 -308 Experimental Results – approximate approach (r=10, ε  10 -308 ) 46 21 66 17 10 25 32 9 6 RPG |PO| 11.003.71194108207C7552 18.0029.4132 C6288 8.340.2567123178C5315 9.384.69502250C3540 8.521.15122140233C2670 6.641.37332533C1908 6.962.21413241C1355 5.160.26452660C880 6.271.71413241C499 7.390.32367 C432 Mem. (MB)Time (s) n=Max TFI |PI| |PO||PI|Circuits

29. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 29 Outline Introduction Previous Work Probabilistic Logic Equivalence Checking –Exact Approach –Approximate Approach Experimental Results Conclusions

30. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 30 Conclusions An aliasing-free assignment procedure is proposed More efficient operations, such as bitwise-AND, bitwise-OR, and shift-add operations are used The aliasing-free assignment and bitwise operations deal with the signal correlation problem well Internal tree-structure replacement is used to reduce the number of required input assignments An approximate approach with configurable aliasing rate is proposed for large circuits

31. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 31 Appendix P.31~P.37

32. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 32 Calculate Signal Probability Transform two input probabilities to their equivalent probability –The denominator is the lowest common multiple of the original denominators The two new numerators conduct bitwise-AND/ bitwise-OR operation to obtain the numerator of output probability if it is an AND/OR gates

33. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 33 Why Work – AND Gate The operation 0101∩0011 is analogous to perform intersection on minterm sets ( ) = ( ) ( ) = ( ) 0 0 1 1 0 1 X 2 X 1 prob. of minterm × × × × (1- ) = = = = 01010101 00110011 ∩ = 00010001 bitwise-AND (1- )

34. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 34 Why Work – OR Gate The operation 10001 ∪ 00101 is analogous to perform union on minterm sets 0 0 1 1 0 1 X 2 X 1 prob. of minterm × × × × = = = = 01010101 00110011 = 01110111 ( ) = ( ) ( ) = ( ) (1- ) ∪ bitwise-OR (1- )

35. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 35 Internal Tree-Structure Replacement (1/2) Only consider two Boolean networks for verification –Internal tree-structure replacement can be used to reduce the number of required assignments –The output probability is changed, but it does not affect the judgement on the equivalence checking

36. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 36 L1=L2 Analysis (2/3) pr(S1 = S2) = pr(L1 = L2) = If S1=S2, then L1=L2 –(1) pr(S1 = S2 ∩ L1 ≠ L2) = 0 pr(S1 = S2 ∩ L1 = L2) + pr(S1 = S2 ∩ L1 ≠ L2) = pr(S1 = S2) = –(2) pr(S1 = S2 ∩ L1 = L2) = (3) ε  pr(S1 ≠ S2 ∩ L1 = L2) = pr(L1 = L2) - pr(S1 = S2) = - (4) pr(S1 ≠ S2 ∩ L1 ≠ L2) = 1 – pr(L1 = L2) = 1 - (1) + (2) + (3) + (4) = 1 S1=S2 L1=L2 S1=S2

37. TH EDA TH EDA NTHU-CS VLSI/CAD LAB 37 Experimental Setup Benchmarks –n<=24 exact approach MCNC benchmarks in BLIF format –n>24 approximate approach ISCAS-85 benchmarks in BLIF format Environment –SIS environment –Sun Blade 2500 workstation Experimental flow –Map benchmarks to the SIS library (22-1.genlib), decompose the networks to AND/OR/NOT gates –Verify the equivalence between original Netlist and Netlist after area optimization (map –m0) –Separate multiple-output network into many single-output subnetworks –BDD based approach - ntbdd_verify_network( N1, N2, DFS_ORDER, ONE_AT_A_TIME )