1. 1 4-BIT ARITHMETIC LOGIC UNIT Motorola MC54/74F181 Heungyoun Kim Lu Gao Jun Li Advisor: Dr. David W. Parent DATE: 12/05/2005

2. 2 Agenda Abstract Introduction –Why –Simple Theory –Background information Summary of Results Project (Experimental) Details Lessons Learned Summary Acknowledgement

3. 3 Abstract The MC54/74F181 is a 4-bit high speed parallel Arithmetic Logic Unit which uses full Carry Lookahead for high speed arithmetic operation. It can perform 16 logic operations or 16 arithmetic operations. We designed a 4-bit ALU that :  Operating frequency = 200 MHz  Area = 340x310  m 2  Power = 15.9mW

4. 4 Introduction The Arithmetic and Logic Unit ( ALU ) is a fundamental block of microprocessor. Design consists of different kinds of logic : Carry Lookahead Adder, AOI, XOR, DFF, NAND, NOR, etc. We can practice all the circuits learned from the textbook. Strictly follow “Design Flow” to understand the Full-Custom design. Provide a good starting point to move on to more advanced IC design.

5. 5 Project Summary We designed a 4-bit ALU based on Motorola MC54/74F181 operating at 200 MHz. Designed the sequential logic circuit: DFF. Total area is 340x310um 2. Power dissipation is 15.9mW.

6. 6 Design Flow and Cost Analysis

7. 7 ALU Block Diagram with Long path

8. 8 MC54/74F181 Function Table

9. 9 Longest Path Calculations  Start with even Tphl (5ns/(13+4)) for each logic level, then reassign Tphl, e.g. steal time from inverter for XOR, to get reasonable WN and WP.  Since AOI33 drives about 135 fF of Cg (fanout is 8), in order to meet timing and at the same time get the reasonable WN and WP, we add two inverters behind AOI33.

10. 10 DFF Sizing

11. 11 Schematic

12. 12 Schematic with DFF (Top-Level)

13. 13 Layout Vdd Gnd RSETCLK DFF Logic

14. 14 Verification(LVS)

15. 15 NC Verilog simulation (Logic) S=0110, A=0000, B=0101  F= A  B = 0101

16. 16 NC Verilog simulation (Arithmetic) S=0110, A=0000, B=0101  F= A minus B minus 1 = 1010

17. 17 Simulations(Logic Function) A 3 A 2 A 1 A 0 = 1010 B 3 B 2 B 1 B 0 = 1001 M=1 Cin=1 --------------------------- S 3 S 2 S 1 S 0 = 1111 F= A = 1010 S 3 S 2 S 1 S 0 =1010 F= B = 1001 S 3 S 2 S 1 S 0 =0101 F= B’ = 0110 S 3 S 2 S 1 S 0 =0000 F= A’ = 0101

18. 18 Simulations(Arithmetic Function) A 3 A 2 A 1 A 0 = 1010 B 3 B 2 B 1 B 0 = 1001 M=0 Cin=1 ----------------------------- S 3 S 2 S 1 S 0 = 1111 F= A minus 1= 1001 S 3 S 2 S 1 S 0 =1010 F= (A+B’) plus AB = 0110 S 3 S 2 S 1 S 0 =0101 F= (A+B) plus AB’ = 1101 S 3 S 2 S 1 S 0 =0000 F= A = 1010

19. 19 POWER Power = 47.77 mW / 3 clocks = 15.9 mW

20. 20 Lessons Learned Organize data and keep track of schedule. Use cell based design and uniform cell height. Draw a floor plan including route of power and major signals before you layout. Do DRC often and LVS for each cell.

21. 21 Summary Our design met all the specifications, speed 200 MHz, area 340 x 310 µm 2, and power dissipation 15.9mW. Learned how to design, simulate and implement static CMOS circuits with delay constraint in transistor level using the AMI06 process. Theory and CDS tool experience learned through this project would be a great stepping stone to the upper level design project and career.

22. 22 Acknowledgements Thanks to our families for all their support. Thanks to Prof. David W. Parent for his help. Thanks to Cadence Design Systems for the VLSI lab. Thanks to Hummingbird for the great remote login.