1. CSE 140L Lecture 4 Flip-Flops, Shifters and Counters Professor CK Cheng CSE Dept. UC San Diego

2. 1)F-F 2)Shift register 3)Counter (Asynchronous) 4)Counter (Synchronous)

3. Flip-Flops DFF D CE C CLR Q CLR CE D C Q 1 X X X 0 0 0 X X No change 0 1 1 1 0 1 0 0 Asynchronous Clear Inputs Output Clock Enable CLK = 0 CLK = 1

4. D Q CLK t t t t setup t hold D Q tcqtcq D-FF Timing

5. Input Timing Constraints Setup time: t setup = time before the clock edge that data must be stable (i.e. not changing) Hold time: t hold = time after the clock edge that data must be stable Aperture time: t a = time around clock edge that data must be stable (t a = t setup + t hold )

6. Output Timing Constraints Propagation delay: t pcq = time after clock edge that the output Q is guaranteed to be stable (i.e., to stop changing) Contamination delay: t ccq = time after clock edge that Q might be unstable (i.e., start changing)

7. Setup Time Constraint The setup time constraint: The maximum delay from register R1 through the combinational logic. The input to register R2 must be stable at least t setup before the clock edge. T c ≥ t pcq + t pd + t setup t pd ≤ T c – (t pcq + t setup )

8. Hold Time Constraint The hold time constraint depends on the minimum delay from register R1 through the combinational logic. The input to register R2 must be stable for at least t hold after the clock edge. t hold < t ccq + t cd t cd > t hold - t ccq

9. 2) A 3 Bit Shift Register D Q CLK D Q D Q 0 0 X X X 11 0 X X 2 0 1 0 X 31 0 1 0 41 1 0 1 50 1 1 0 60 0 1 1 71 0 0 1 Time Steps A B C D A B C D Signal A is given as input.

10. 3) A 3 Bit Counter (Asynchronous) T Q CLK T Q T Q t A C B t t 1 010 110 B C t 1 1 7 6 5 4 A 1 1 1 Reset A(0) = B(0) = C(0) = 0 0 0 0 0 0 11 1 1 7 2 1 1 0 6 31 0 1 5 41 0 0 4 50 1 1 3 60 1 0 2 70 0 1 1 Time C B A