1. Lecture 5#1#1 הודעה לשבוע הבא !  שבוע הבא אני לא נימצא  המתרגל ניר אנדלמן יעביר את השיעור  לא ילמד חומר חדש  נוכחות רשות !

2. Switching Units

3. Lecture 5#3#3 Types of switching elements  Telephone switches m switch samples  Datagram routers m switch datagrams  ATM switches m switch ATM cells INPUTS OUTPUTS

4. Lecture 5#4#4 Repeaters, bridges, routers, and gateways  Repeaters/Hubs: at physical level (L1)  Bridges: at datalink level (L2) m based on MAC addresses m discover attached stations by listening  Routers: at network level (L3) m participate in routing protocols  Application level gateways: at application level (L7) m treat entire network as a single hop  Gain functionality at the expense of forwarding speed m for best performance, push functionality as low as possible

5. Lecture 5#5#5 Types of services  Packet vs. circuit switches m packets have headers and samples don’t  Connectionless vs. connection oriented m connection oriented switches need a call setup m setup is handled in control plane by switch controller m connectionless switches deal with self- contained datagrams

6. Lecture 5#6#6 Other switching unit functions  Participate in routing algorithms m to build routing tables m Next Lecture!  Resolve contention for output trunks m buffer scheduling m Previous Lecture!  Admission control m to guarantee resources to certain streams

7. Lecture 5#7#7 Requirements  Capacity of switch is the maximum rate at which it can move information, assuming all data paths are simultaneously active  Primary goal: maximize capacity m subject to cost and reliability constraints  Circuit switch must reject call if can’t find a path for samples from input to output m goal: minimize call blocking  Packet switch must reject a packet if it can’t find a buffer to store it awaiting access to output trunk m goal: minimize packet loss  Subgoal: Don’t reorder packets

8. Lecture 5#8#8 Internal switching  In a circuit switch, path of a sample is determined at time of connection establishment m No need for a sample header--position in frame is enough  In a packet switch, packets carry a destination field m Need to look up destination port on-the-fly  Datagram m lookup based on entire destination address  Cell m lookup based on VCI – used as an index to a table  Other than that, switching units are very similar

9. Lecture 5#9#9 Blocking in packet switches  Can have both internal and output blocking  Internal m no path to output m Example: head of line blocking.  Output m output link busy  If packet is blocked, must either buffer or drop it

10. Lecture 5#10 Dealing with blocking  Overprovisioning m internal links much faster than inputs  Buffers m at input or output  Backpressure m if switch fabric doesn’t have buffers, prevent packet from entering until path is available  Parallel switch fabrics m increases effective switching capacity

11. Lecture 5#11 Three generations of packet switches  Different trade-offs between cost and performance  Represent evolution in switching capacity, rather than in technology m With same technology, a later generation switch achieves greater capacity, but at greater cost  All three generations are represented in current products

12. Lecture 5#12 First generation switch  Most Ethernet switches and cheap packet routers  Bottleneck can be CPU, host-adaptor or I/O bus, depending computer queues in memory CPU linecard

13. Lecture 5#13 Second generation switch  Port mapping intelligence in line cards  Bottleneck is the bus (or ring) bus computer front end processors or line cards

14. Lecture 5#14 Third generation switches  Third generation switch provides parallel paths (fabric) NxN packet switch fabric OLC IN ILC OUT

15. Lecture 5#15 Third generation (contd.)  Features m self-routing fabric m output buffer is a point of contention unless we arbitrate access to fabric m potential for unlimited scaling, as long as we can resolve contention for output buffer

16. Switching - Fabric

17. Lecture 5#17 Switching: abstract model Number of connections: from few (4 or 8) to huge (100K)

18. Lecture 5#18 Internal Non-Blocking Types  Re-arrangeable m Can route any permutation from inputs to outputs.  Strict sense non-blocking m Given any current connections through the switch. m Any unused input can be routed to any unused output.  Wide sense non-blocking. m There exists a specific routing algorithm, s.t., m for any sequence of connections and releases, m Any unused input can be routed to any unused output, m assuming all the sequence was served by the routing algorithm.

19. Lecture 5#19 Multiplexors and demultiplexors  Multiplexor: aggregates sessions m N input lines m Output runs N times as fast as input  Demultiplexor: distributes sessions m one input line and N outputs that run N times slower  Can cascade multiplexors De-Mux 12N12N 12N12N 1 2 N MUX

20. Lecture 5#20 Time division switching  Key idea: when demultiplexing, position in frame determines output link  Time division switching interchanges sample position within a frame: m Time slot interchange (TSI) MUXMUX DEMUXDEMUX TSI

21. Lecture 5#21 Time Slot Interchange (TSI) : example sessions: (1,3) (2,1) (3,4) (4,2) 4 3 2 1 3 1 4 2 12341234 Read and write to shared memory in different order

22. Lecture 5#22 TSI  Simple to build.  Multicast: easy (why?)  Limit is the time taken to read and write to memory  For 120,000 telephone circuits m Each circuit reads and writes memory once every 125 ms. m Number of operations per second : 120,000 x 8000 x2 m each operation takes around 0.5 ns => impossible with current technology  Need to look to other techniques

23. Lecture 5#23 Space division switching  Each sample takes a different path through the switch, depending on its destination  Crossbar: Simplest possible space-division switch  Crosspoints can be turned on or off inputsinputs outputs

24. Lecture 5#24 Crossbar - example 1 2 3 4 123 4 sessions: (1,2) (2,4) (3,1) (4,3)

25. Lecture 5#25 Crossbar  Advantages: m simple to implement m simple control m strict sense non-blocking m Multicast  Drawbacks m number of crosspoints, N 2 m large VLSI space m vulnerable to single faults

26. Lecture 5#26 Time-space switching  Precede each input trunk in a crossbar with a TSI  Delay samples so that they arrive at the right time for the space division switch’s schedule Crosspoint: 4 (not 16) memory speed : x2 (not x4) 2 1 4 3 MUXMUX MUXMUX 1 2 3 4 TSI 1 2 4 3 DeMux

27. Lecture 5#27 Finding the schedule  Build a routing graph m nodes - input links m session connects an input and output nodes.  Feasible schedule  Computing a schedule m compute perfect matching. 1212 3434 1212 3434

28. Lecture 5#28 Time-Space: Example 2 1 4 3 TSI 2 1 3 4 3131 2424 Internal speed = double link speed time 1 time 2

29. Lecture 5#29 Time-space-time (TST) switching  Allowed to TSI both on input and output  Gives more flexibility => lowers call blocking probability TSI

30. Lecture 5#30 Circuit switching - Space division  graph representation m transmitter nodes m receiver nodes m internal nodes  Feasible schedule m edge disjoint paths.  cost function m number of crosspoints (complexity of AxB is AB) m internal nodes

31. Lecture 5#31 Crossbar - example 1 2 3 4 123 4

32. Lecture 5#32 Another Example

33. Lecture 5#33 Another Example sessions: (1,3) (2,6) (3,1) (4,4) (5,2) (6,5)

34. Lecture 5#34 Clos Network Clos(N, n, k) : N - inputs/outputs; cross-points: 2 (N/n)nk + k(N/n) 2 nxk(N/n)x(N/n) kxn N=6 n=2 k=2 3x3 2x2 N k

35. Lecture 5#35 Clos Network - strict sense non-blocking  Holds for k  2n-1  Proof: m Consider an idle input and output m Input box connected to at most n-1 middle layer switches m output box connected to at most n-1 middle layer switches m There exists an ”unused" middle switch good for both. n x k k x n n-1

36. Lecture 5#36 Example Clos(8,2,3) N=8 n=2 k=3 4x4 3x2 2x3 4x43x2 Need to route a new call

37. Lecture 5#37 Clos Network nxk(N/n)x(N/n) kxn N=6 n=2 k=2 3x3 2x2 Why is k=n internally blocking?

38. Lecture 5#38 Clos Network - re-arrangable  Holds for k  n  Proof: m Consider the routing graph. m find a perfect matching. m route the perfect matching through a single middle switch! m remaining network is Clos(N-N/n,n-1,k-1)  summary: m smaller circuit m weaker guarantee  Multicast ? 1212 3434 1212 3434

39. Lecture 5#39 Recursive Construction: basis The basic element: The two states: The dimension: r=0

40. Lecture 5#40 Recursive Construction: Benes Network r-1 dimension N/2 size r-1 dimension N/2 size

41. Lecture 5#41 Example 16x16

42. Lecture 5#42 Benes Networks  Symmetry  Size: m F(N) = 2(N/2)*4 + 2F(N/2) = O(N log N)  Rearrangable m Clos network with k=2 n=2  Proof I: m Build routing graph. m Find 2 matchings m route one in the upper Benes and the other in the lower.

43. Lecture 5#43 Greedy permutation routing  Start with an arbitrary node i 1 m set i 1 to upper.  At the output, o 1, a new constraint, m set o 2 to lower.  Continue until no new constraint. m Completing a cycle.  Continue until done.  Solve for the upper and lower Benes recursively.

44. Lecture 5#44 Example: Benes Network for r=2 level 0 switches level 2r switches I1I1 I2I2 1234567812345678

45. Lecture 5#45 Example level 0 switches level 2r switches I1I1 I2I2 1234567812345678 1 2 3 4 5 6 7 8 1 5 6 8 4 2 3 7 ( )

46. Lecture 5#46 Example level 0 switches level 2r switches I1I1 I2I2 1234567812345678 1 2 3 4 5 6 7 8 1 5 6 8 4 2 3 7 ( )

47. Lecture 5#47 Example level 0 switches level 2r switches I1I1 I2I2 1234567812345678 1 2 3 4 5 6 7 8 1 5 6 8 4 2 3 7 ( )

48. Lecture 5#48 Example level 0 switches level 2r switches I1I1 I2I2 1234567812345678 1 2 3 4 5 6 7 8 1 5 6 8 4 2 3 7 ( )

49. Lecture 5#49 Strict Sense non-Blocking N/2 x N/2............

50. Lecture 5#50 Properties  Size: m F(N) = 2N*6 + 3F(N/2) = O( N 1.58 ) m strict sense non-blocking m Clos network with k=3 n=2  Better parameters: m n=sqrt{N}, k=2sqrt{N}-1 m recursive size sqrt{N} x sqrt{N} m Circuit size N log 2.58 N

51. Lecture 5#51 Cantor Networks  m copies of Benes network.  For m = log N its strict sense non-blocking  Network size N log 2 N  Example

52. Lecture 5#52 Cantor Network m=4

53. Lecture 5#53 Proof Sketch:  Benes network: 2 log N -1 layers, N/2 nodes in layer. Middle layer= layer log N -1  Consider the middle layer of the Benes Networks.  There are Nm/2 nodes in in all of them combined.  Bound (from below) the number of nodes reachable from an input and output.  If the sum is more than Nm/2: m There is an intersection m there has to be a route.

54. Lecture 5#54 Proof Sketch:  Let A(k) = number of nodes reachable at level k.  A(0)=m  A(1)= 2A(0)-1  A(2)=2A(1)-2  A(k)=2A(k-1) - 2 k-1 = 2 k A(0) - k 2 k-1  A(log N -1) = Nm/2 - (log N -1) N/4  Need that: 2A(log N -1) > Nm/2. m 2[Nm/2 - (log N -1) N/4] > Nm/2.  Hold for m> log N-1.

55. Lecture 5#55 Proof Sketch:  Let A(k) = number of nodes reachable at level k.  A(0)=m  A(1)= 2A(0)-1  A(2)=2A(1)-2  A(k)=2A(k-1) - 2 k-2 = 2 k-1 A(1) - (k-1) 2 k-2  A(log N) = Nm/2 - (log N -1) N/4  Need that: 2A(log N) > Nm/2.  Hold for m> log N-1.

56. Lecture 5#56 Advanced constructions  There are networks of size O(N log N). m the constants are huge!  Basic paradigm also applies to large packet switches.