1. Team W3: Anthony Marchetta Derek Ritchea David Roderick Adam Stoler Milestone 3: Feb. 4 th Size Estimates/Floorplan Overall Project Objective: Design an Air-Fuel Ratio Controller for a small gasoline engine with low emissions and low cost Design Manager: Steven Beigelmacher

2. Status Design Proposal (done) Architecture (done) High Level C Simulation Behavioral Verilog & Test Bench Final Algorithm & Major Functional Components Floorplan & Structural Verilog (done) Not yet simulated To be done Gate Level Design Component Layout Chip Layout SPICE Simulation of Entire Chip

3. Design Decisions (before) Look-up tables and comparing values for look-up tables programmable. 7 SRAM blocks (1 8x8, 2 8x1, 4 7x1) Fixed point Multiplier for decimal numbers Increment output register to know when multiplications are completed

4. Design Decisions (after) Look-up tables and comparing values for look-up tables programmable. 2 SRAM blocks (1 8x10, 1 7x4) Fixed point Multiplier for decimal numbers (same) Increment output register to know when multiplications are completed (same) Only one comparator is needed along with more control logic.

5. SRAM Design Writing to SRAM Drive B and ~B with in and ~in Assert select line Value will be latched Reading from SRAM Assert precharge on positive edge Assert select on negative edge Low side will discharge through transistors to GND High side will remain high Transistor sizing T3 must have larger resistance than T1 (narrower transistor) so value won’t be erased on read Same for T4 and T2

6. SRAM Design One 7x4 Block for Comparator Values –Sequential accesses for comparison (only 1 comparator) –Results stored in registers One 8x10 Block for Look-Up Tables All entries will be 12-bit entries –Done in bit slices for simplified interconnect Comp Value 0 1 2 3 4 5 6 Bit Number 0 1 2 3 4 5 6 7 8 9 10 11 speed load throttle oxygen Comparator Value Table

7. SRAM Layout 6 um 3 um Individual Cell 8 x (10x12) Lookup Table 48 um 360 um ROWDECROWDEC Column Decoder MUX 7 x (4x12) Comparator Table 42 um 144 um ROWDECROWDEC Column Decoder MUX 144 um

8. Comparator Design For least significant bit: For most significant bit:

9. Alternate Comparator Design Subtractor Look at the sign bit to see which input is greater This design requires that your inputs and look-up table values be 2C encoded. Or it requires that you add a sign bit or do a conversion This would significantly change our design. RC Adder 12 Over- flow sign vdd

10. 12bit Input Reg 8X8 SRAM Look-up 12bit Input Reg Engine Speed Manifold Pressure 8X1 SRAM Look-up 12bit Input Reg Throttle Position 8X1 SRAM Look-up 12bit Input Reg %Oxygen 7X1 L.U. Fixed Point Array Multiplier 2:1Mux 12bit Output Shift Register Control Logic OUTPUT 7X1 L.U. before

11. 12bit Input Reg 8X10 SRAM Value Look-up 12bit Input Reg Engine Speed Manifold Pressure 12bit Input Reg Throttle Position Fixed Point Array Multiplier 2:1M ux 12bit Output Shift Register Control Logic 12bit Input Reg %Oxygen 7X4 SRAM Comparator Look-up 4:1Mux = 3bit register 12bit Register after

12. Floorplan Basic Parts FA - 18µm X 11µm HA - 5µm X 7µm DFF - 21µm X 20µm Xor - 10µm X 7µm These estimates are from downsizing 322 Fall 2002 layouts.

13. Floorplan Multiplier 210µm 220µm ……. 11fq 11hq 144qndgqtes ha 9FA

14. Floorplan 300µm Registers and control logic 400µm Total area: 120,000µm 2 density: 0.13 trans/µm 2 7X4 SRAM 8X10 SRAM Multiplier Comparator

15. Metal Directionality

16. Updated Transistor Count Registers (5 12-bit, shift)2,568 SRAMS (1 8x10, 1 7x4)6,720 Comparator410 MUXs (2)696 Control Logic1,000 12-bit FP Multiplier3,096 Decoders1,000 TOTAL difference 15,490 -1,958

17. Problems Figuring out how to optimize the comparisons Optimizing the control logic

18. Questions????