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REDUCED POWER SHIFT REGISTER WITH MULTIPHASE CLOCKS ELEC 6270 Kannan Govindasamy.

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Presentation on theme: "REDUCED POWER SHIFT REGISTER WITH MULTIPHASE CLOCKS ELEC 6270 Kannan Govindasamy."— Presentation transcript:

1 REDUCED POWER SHIFT REGISTER WITH MULTIPHASE CLOCKS ELEC 6270 Kannan Govindasamy

2 OUTLINE Objective Simulation Specification Background information ImplementationResultsConclusion

3 OBJECTIVE Design and Verify a 32 bit Shift Register with Multi-phase Clocks Study Low Voltage Power and Delay characteristics

4 Simulation Specification TechnologyTsmc035 Rated Voltage 5v NMOS Vth.54v PMOS Vth -.64V Temperature 27 C Degree Simulator ELDO ver 6.3.11

5 Background Information Dynamic Signal transitions Signal transitions Logic activity Glitches Short-circuit Short-circuitStatic Leakage Leakage

6 Shift Registers with Multiphase clocks

7 Multiphase Clock Generators Modified Johnson counter is used for Multiphase Clock generation

8 ELDO SIMULATION

9 Results Power Table N=1 Voltage Avg Power ObservedTheoreticalPower 58.4288mW- 31.98mW3.034mW 2643.5uW1.24mW 1148.4uW337.2uW.9115.7uw270.4uW

10 Results Power Table N=4 Voltage Avg Power ObservedTheoreticalPower 55.08mW- 31.47mW1.828mW 2583.5uW812.8uW 1116.2uW203.6uW.986.33uw164.5uW

11 Results Delay Table for N=1 VoltageDelay Observed (ns) Delay Calculated (ns) 5.72- 3.83.78 2.96.89 18.21.42.922.81.60

12 Power vs Voltage

13 Delay vs Voltage Plot

14 Power-Delay Plot

15 Power Consumption vs Parallelism Degree of Parallelism Freq Power (mW) 1100MHz8.42 250MHz6.92 425MHz5.08 812.5MHz4.63 166.25MHz4.71

16 Summary A power reduction of 39.1% is achieved when degree of parallelism is 4. A power reduction of 45.07% is achieved for N=8. for further parallelism power reduction gets stabilized

17 Reference ELEC 6270 class slides by Dr.Agrawal Tsung-chu Huang, Kuen-Jong Lee, A Low-Power LFSR Architecture, Test symposium 2001

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