1. 1 Simple FPGA David, Ronald and Sudha Advisor: Dave Parent 12/05/2005

2. 2 Agenda Abstract Introduction –Why? –Simple Theory –Back Ground information Summary of Results Project Details Results Cost Analysis Conclusions

3. 3 Abstract We designed an FPGA with –3 Programmable 2-input Look-up Tables (LUT) –2 Flip Flops –2 Inputs and 2 Outputs Clock Frequency: up to 242 MHz Area: slightly under 400x400  m 2 Power: Still being tested

4. 4 Introduction FPGA is a digital circuit that can be “programmed” and “reprogrammed” to behave as different digital circuits. Four applications that can be implemented in the simple FPGA. –Mod 2 counter (designed and tested) –3 sequential 1’s pattern match detector (designed) –Clock divider (x2) (designed) –1 bit ALU with no carry in (designed) Why? –Try something different

5. 5 Project Details Components: –Two LUTs (Look up Tables) Five Latches, Four 2X1 MUXs, One Flip Flop per LUT –One LUT2c (Only combinational logic) Four Latches and One 2X1 MUX per LUT2c –One Interconnection Switch 9 Latches and 9 Transmission Gates LUT2 architecture: –Latches hold the truth table values –Inputs IN0 and IN1 are the control signals to control the MUX –The output of the LUT can be combinational or registered.

6. 6 LUT Schematic Abstract Q FF 2X1 In0 In1 CLK Out Register Select Programmable Gate

7. 7 LUT2 Architecture with synchronous clear 4 x 1 FF 2 IN[1:0] CLK OUT LATCHES 012R 2 x 1 0 3 CLEAR 2 x 1

8. 8 Switch Switch uses the latches to program transmission gates that connects inputs to outputs.

9. 9 Switch Architecture LUT2-A CLR LUT2-A IN1 LUT2-A IN0 LUT2-A Y LUT2-B CLR LUT2-B IN1 LUT2-B IN0 LUT2-B Y LUT2-C IN1 LUT2-C IN0 LUT2-C Y VDD IB-0 IN_X IB-1 IN_X OB-0 OUT_X OB-1 OUT_X Transmission Gate with Control Latch sw_clr sw_in1 sw_in0

10. 10 Verification

11. 11 Longest Path Calculations Note: All widths are in microns, capacitances in fF, time in ns.

12. 12 Schematic

13. 13 Layout

14. 14 LVS

15. 15 Simulations We performed worst case SPICE simulations of each gate in the worst case path and summed up. Worst Case SPICE at top level not done –Time Ran Out!! –SPICE simulation at top level is cumbersome due to need to program FPGA prior to running simulation.

16. 16 Cost Analysis Estimate how much time you spent on each phase of the project –verifying logic – 10 hours –verifying timing – 2 hours –Layout – 30 hrs –post extracted timing – 2 hrs

17. 17 Lessons Learned Set deadlines for project components to be due and set specs for each project component. Hold weekly meetings to discuss status/issues and make sure all members are on same page. Don’t take 124 and 166 in the same semester, not enough time in the day.

18. 18 Summary Programming an FPGA was an interesting experience but designing one was exciting. To learn more about using FPGAs take EE178.

19. 19 Acknowledgements Thanks to Cadence Design Systems for the VLSI lab Thanks to Synopsys for Software donation even though we didn’t use your software Thanks to Professor Dave Parent for advice on Layout