1. Nov. 29, 2005 ELEC6970-001 Class Presentation 1 Logic Redesign for Low Power ELEC 6970 Project Presentation By Nitin Yogi

2. Nov. 29, 2005ELEC6970-001 Class Presentation2 Outline Low Power Logic Synthesis Low Power Logic Synthesis Low Power Optimization Techniques Low Power Optimization Techniques Redundancy Insertion Redundancy Insertion Logic Transformation Logic Transformation Multiplier Cell Optimization Multiplier Cell Optimization Experimental Results Experimental Results Summary and Conclusion Summary and Conclusion What I learnt ! What I learnt !

3. Nov. 29, 2005ELEC6970-001 Class Presentation3 Low Power Logic Synthesis Sources of Power Sources of Power  Dynamic power Signal transitions Signal transitions Logic activity Logic activity Glitches Glitches Short-circuit Short-circuit  Static Leakage Leakage Power α Area Power α Area  Method : Area optimized logic synthesis Power α Transistor Leakage and Short-circuit current Power α Transistor Leakage and Short-circuit current  Method : Optimized transistor level design for gates Power α Signal Activity of Circuit Power α Signal Activity of Circuit  Method : Low Power Logic Synthesis

4. Nov. 29, 2005ELEC6970-001 Class Presentation4 Low Power Optimization techniques Technology Independent Optimization Technology Independent Optimization  Algebraic Logic Restructuring  Kernel and Cube Extraction  Iterative extraction and re-substitution of sub- expressions Post Mapping Structural Optimization Post Mapping Structural Optimization  Redundancy Insertion  Logic Transformations

5. Nov. 29, 2005ELEC6970-001 Class Presentation5 Post-mapping Structural Optimization Redundancy Insertion Redundancy is inserted into the circuit to minimize a cost function. Redundancy is inserted into the circuit to minimize a cost function. 3 elements required in the process 3 elements required in the process Suitable circuit location for redundancy insertion Suitable circuit location for redundancy insertion Candidate type of redundancy Candidate type of redundancy Cost function Cost function 3 steps involved 3 steps involved Identifying candidates for redundancy insertion at a suitable circuit location for minimum cost function. Identifying candidates for redundancy insertion at a suitable circuit location for minimum cost function. Applying logic transformation to insert redundancy Applying logic transformation to insert redundancy Reducing the circuit by removing other generated redundancies by logic transformation. Reducing the circuit by removing other generated redundancies by logic transformation.

6. Nov. 29, 2005ELEC6970-001 Class Presentation6 Post-mapping Structural Optimization Finding Circuit Locations for Redundancy Insertion Finding Circuit Locations for Redundancy Insertion Identify Source and Target locations using don’t care implications Identify Source and Target locations using don’t care implications A C Y 0 0 B x x x D x x Source location Possible target location

7. Nov. 29, 2005ELEC6970-001 Class Presentation7 Candidate Redundancy insertions Candidate Redundancy insertions Redundancy insertions to input of gates Redundancy insertions to input of gates Used to reduce signal activity at the output of a gate using another signal. Used to reduce signal activity at the output of a gate using another signal. Post-mapping Structural Optimization 0 1 x x ‘0’ implication don’t care ‘1’ implication don’t care

8. Nov. 29, 2005ELEC6970-001 Class Presentation8 Post-mapping Structural Optimization Gate Insertion: Gate Insertion:

9. Nov. 29, 2005ELEC6970-001 Class Presentation9 Post-mapping Structural Optimization Circuit Reduction to eliminate unwanted redundancies Circuit Reduction to eliminate unwanted redundancies Redundancy identification methods: Redundancy identification methods: ATPG based ATPG based Use of exhaustive ATPG to find redundant faults Use of exhaustive ATPG to find redundant faults Redundant faults signify redundant logic Redundant faults signify redundant logic Fault independent Fault independent Controllability and Observability analysis Controllability and Observability analysis

10. Nov. 29, 2005ELEC6970-001 Class Presentation10 Post-mapping Structural Optimization Logic Transformations Permissible function: Permissible function: If all the network primary output functions do not change after the function realized at a signal line Li is replaced by a function f, then the function f is called a permissible function for the signal line Li. If all the network primary output functions do not change after the function realized at a signal line Li is replaced by a function f, then the function f is called a permissible function for the signal line Li. Gate Substitution Gate Substitution Replace a target signal line with the candidate signal line having the same function. Replace a target signal line with the candidate signal line having the same function. Inverter Insertion Inverter Insertion Replace a target signal line with the inverted candidate signal line having the same function. Replace a target signal line with the inverted candidate signal line having the same function.

11. Nov. 29, 2005ELEC6970-001 Class Presentation11 Post-mapping Structural Optimization Logic Transformations Eliminate inverters on signals with high activity Eliminate inverters on signals with high activity Discourage the implementation of EX-OR gates Discourage the implementation of EX-OR gates EX-OR gate example: EX-OR gate example: Y = AB + AB Y = AB + AB = (AB) + (AB) = (AB) + (AB) = (A + B) + AB = (A + B) + AB

12. Nov. 29, 2005ELEC6970-001 Class Presentation12 Multiplier Cell Full Adder

13. Nov. 29, 2005ELEC6970-001 Class Presentation13 Multiplier Cell EX-OR

14. Nov. 29, 2005ELEC6970-001 Class Presentation14 Multiplier Cell Modified EX-OR

15. Nov. 29, 2005ELEC6970-001 Class Presentation15 Multiplier Cell Modified - 2

16. Nov. 29, 2005ELEC6970-001 Class Presentation16 Multiplier Cell Leonardo (delay optimized)

17. Nov. 29, 2005ELEC6970-001 Class Presentation17 Multiplier Cell Leonardo (area optimized)

18. Nov. 29, 2005ELEC6970-001 Class Presentation18 Experimental Results Multiplier Cell Design and simulation details Design and simulation details Design Entry tool: Design Architect Design Entry tool: Design Architect Simulation tool : Eldo (timing and power analysis) Simulation tool : Eldo (timing and power analysis) Technology library: tsmc 0.18um (V DD = 1.8V) Technology library: tsmc 0.18um (V DD = 1.8V) Input Vectors: Input Vectors: Inputs: frequencies in multiples of 2 Inputs: frequencies in multiples of 2 Output transitions generated: Output transitions generated: Sum Out (Sout) : 25 Sum Out (Sout) : 25 Carry Out (Cout) : 12 Carry Out (Cout) : 12

19. Nov. 29, 2005ELEC6970-001 Class Presentation19 Multiplier Cell Results Unopt.Opt.Leo_AreaLeo_Delay Static Power 367.04 pW 201.93 pW 168.94 pW 194.28 pW Dyn. Power 27.08 uW 17.39 uW 20.83 uW 21.28 uW T delay (A/B=>Sout) Avg. 276.13 ps 287.77 ps 225.85 ps 189.16 ps Peak 328.45 ps 345.74 ps 257.23 ps 255.17 ps T delay (A/B=>Cout) Avg. 226.08 ps 173.77 ps 80.59 ps 90.16 ps Peak 237.07 ps 177.02 ps 108.62 ps 96.60 ps

20. Nov. 29, 2005ELEC6970-001 Class Presentation20 Summary and Conclusion Post Mapped Structural Optimization techniques for Low Power prove to be effective. Post Mapped Structural Optimization techniques for Low Power prove to be effective. Percentage reduction in power consumption of optimized Multiplier Cell as compared to: Percentage reduction in power consumption of optimized Multiplier Cell as compared to: Unoptimized cell: ~35.7% Unoptimized cell: ~35.7% Leonardo generated: ~15% Leonardo generated: ~15% Percentage increase in critical path delay of optimized Multiplier Cell as compared to: Percentage increase in critical path delay of optimized Multiplier Cell as compared to: Unoptimized cell: ~35.7% Unoptimized cell: ~35.7% Leonardo generated: ~50% Leonardo generated: ~50% Effective cost functions to include delay constraints will enhance the quality of the circuits. Effective cost functions to include delay constraints will enhance the quality of the circuits. Effective algorithms for structural optimization. Effective algorithms for structural optimization. 32 x 32 bit Multiplier power optimization. 32 x 32 bit Multiplier power optimization.

21. Nov. 29, 2005ELEC6970-001 Class Presentation21 What I learnt ! Low Power Logic Synthesis Low Power Logic Synthesis Logic synthesis Logic synthesis Logic optimization Logic optimization Redundancy insertion, identification and elimination Redundancy insertion, identification and elimination Use of EDA tools for timing and power analysis Use of EDA tools for timing and power analysis Start your projects early! (wish I would have) Start your projects early! (wish I would have) Large patience required with EDA tools! Large patience required with EDA tools!

22. Nov. 29, 2005ELEC6970-001 Class Presentation22 References 1. S. Devadas, S. Malik, “A Survey of Optimization Techniques Targeting Low Power VLSI Circuits,” Annual ACM IEEE Design Automation Conference, Proceedings of the 32nd ACM/IEEE conference on Design automation, San Francisco, California, United States, pp. 242 – 247, 1995 2. Pradhan D.K., Chatterjee M., Swarna M.V., Kunz W, “Gate-level synthesis for low- power using new transformations,” Low Power Electronics and Design, 1996, International Symposium on, pp 297-300, Aug 1996 3. Wang Q., Vrudhula S.B.K., “Multi-level logic optimization for low power using local logic transformations,” Computer-Aided Design, 1996. ICCAD-96., 1996 IEEE/ACM International Conference on 10-14 Nov. 1996 Page(s):270 – 277 4. Shih-Chieh Chang, Marek-Sadowska M, “Perturb And Simplify: Multi-level Boolean Network Optimizer,” Computer-Aided Design, 1994., IEEE/ACM International Conference on November 6-10, 1994 Page(s):2 - 5 5. R. V. Menon, S. Chennupati, N. K. Samala, D. Radhakrishnan and B. Izadi, “Power Optimized Combinational Logic Design,” Proceedings of the International Conference on Embedded Systems and Applications, pp. 223 - 227, June 2003. 6. W. Kunz, “Multi-level Logic Optimization By Implication Analysis,” Computer- Aided Design, 1994., IEEE/ACM International Conference on November 6-10, 1994 Page(s):6 - 13

23. Nov. 29, 2005ELEC6970-001 Class Presentation23 References 7. Roy K., Prasad S.C., “Circuit activity based logic synthesis for low power reliable operations,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 1, Issue 4, Dec. 1993, pp 503 – 513 8. Ki-Wook Kim, Ting Ting Hwang, Liu C.L., Sung-Mo Kang, “Logic transformation for low power synthesis,” Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings, pp158 – 162, March 1999 9. Brzozowski I., Kos A., “Minimisation of power consumption in digital integrated circuits by reduction of switching activity,” EUROMICRO Conference, 1999. Proceedings. 25 th Volume 1, 8-10 Sept. 1999 Page(s):376 - 380 vol.1 M. A. Iyer and M. Abramovici, “Low-Cost Redundancy Identification for Combinational Circuits,” in Proc. 7th International Conf. on VLSI design, pp. 315- 317, January 1994. 10. V.D. Agrawal; M.L. Bushnell, Qing Lin, “Redundancy identification using transitive closure,” Test Symposium, 1996., Proceedings of the Fifth Asian 20-22 Nov. 1996 Page(s):4 – 9 11. Abramovici M., Iyer M.A., “One-Pass Redundancy Identification and Removal,” Test Conference, 1992. Proceedings., International Sept. 20-24 1992 Page(s):807

24. Nov. 29, 2005ELEC6970-001 Class Presentation24 Thank You! Questions ???