1. FIR Filter CMPE 222 – Project Divya Misra Gnanapriya Mohanavelu

2. FIR Filter

3. Aim of the project Study the effect of latency Study the effect of type of adders on area&timing Understanding the synopsys tool Effect of taps on filters

4. Terms used Coefficients Taps –Memory –No. of calculations –Filtering –Advantages Stop band attenuation Less ripple Narrower filter

5. 3-tap filter

6. Actual timing diagram

7. 3-tap filter Architecture

8. What we did Combinational circuit for addition –Synthesis (had problems) All multiplications in the same stage Feeding constants externally –Synthesis (had problems)

9. Timing diagram with latency 5

10. Timing Diagram after reducing the latency to 3

11. Timing Diagram after increasing the latency to 6

12. Latency 3 clock cycles 5 clock cycles 6 clock cycles Area79051.8969508.4579051.89 Timing9.61 map_effort = medium + boundary optimization

13. Synthesis list command –Lists information about the commands,variables and licenses in the design analyzer or standard dc_shell –e.g.: list link_library link_library = {"typical.db"}

14. Shell script used for synthesis %dc_shell free –design alias veri “read –f verilog” veri fir.v veri fir_ctrl.v veri fir_dp.v link compile –map_effort medium –boundary_optimization

15. Changing the type of adder dc_shell>current_design fir_dp dc_shell> report_resources Implementation Report ========================================================================== | | | Current | Set | | Cell | Module | Implementation | Implementation | =========================================================================== | mult_30 | DW02_mult | csa | | | mult_36 | DW02_mult | csa | | | r124 | DW01_add | rpl | | ========================================================================== dc_shell>set_implementation clf r124 dc_shell> report_resources

16. Changing the type of adder (contd.) Implementation Report ========================================================================== | | | Current | Set | | Cell | Module | Implementation | Implementation | =========================================================================== | mult_30 | DW02_mult | nbw | | | mult_36 | DW02_mult | wall | | | r124 | DW01_add | clf | clf | ==========================================================================

17. Area and Timing Carry Look Forward Ripple Carry Adder Area72023.2169508.45 Timing8.909.61

18. sample c0 16-tap filter DDDD ++++ c3c2c1c15 result

19. Logic used A = sum0+sum1 +sum2+sum3 D = sum12+sum13 +sum14+sum15 C = sum8+sum9 +sum10+sum11 B = sum4+sum5 +sum6+sum7 Result =A+B+C+D

20. Timing Diagram

21. Area & timing Area = 985775.25 Timing = 9.77