1. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang Research Summary of Oregon State University Patrick Chiang Email: pchiang@eecs.oregonstate.edupchiang@eecs.oregonstate.edu Website: http://eecs.oregonstate.eduhttp://e www.ece.oregonstate.edu

2. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang Summary Overview of Oregon State My Current Research Interests –High Frequency (> 20GHz) Serial Links –Low power (< 1Gbs/mW) signaling –High Sampling Rate (> 20GS/s), Low Resolution ADC Tsinghua Research –Low Power(< 2mW), Low Voltage(< 1V) RF Receiver –Programmable, Redundant, Self-healing RF Circuit Design with On-Die Calibration

3. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang Life at Oregon State University Location Beautiful surroundings Oregon is high tech center –Intel –Mentor Graphics –Synopsys Main Hall, OSUMt. Hood, Oregon Oregon State Stanford, Berkeley UCLA, Caltech Intel Hillsboro, Oregon

4. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang Mixed-Signal Faculty Gabor Temes Un-Ku Moon Terri Fiez Karti Mayaram Andreas Weisshaar Raghu Settaluri Huaping Liu Zhongfeng Wang Extensible communication & low power DSP architectures Signal integrity, interconnects, packaging, passives Substrate coupling Self correcting RF/analog design in scaled technologies Patrick Chiang Pavan Hanumolu

5. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang Why Oregon State Mixed-Signal is Recognized Top quality faculty –More than 500 journal and conference publications –More than 12 editors/associate editors –More than 5 books and 13 books chapters –4 Fellows of the IEEE Top quality graduate students –Over 200 graduate students in mixed-signal integration Strong external collaboration –MIT, Illinois, Stanford, Berkeley, U Washington, Harvard National Semiconductor, Texas Instruments, Analog Devices, Intel, Cypress Semiconductor, AKM, Boeing, SRC, CDADIC, Crystal Semiconductor, Motorola, Silicon Labs, DARPA, AFRL, Honeywell, Tektronix, Sandia National Labs, Cadence “OSU has one of the nation’s leading research programs on analog and mixed-signal design.” Dave Hodges, former Dean of Engineering, UC Berkeley VLSI Circuits Symposium 2006 # of Papers – 111 Oregon State – 9 Berkeley – 7 UCLA – 5 UCSD – 2 Stanford – 2 MIT – 1

6. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang New Momentum for Growing Program New Building, Sep. 2005 http://engr.oregonstate.edu/top25/building/

7. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang Summary Overview of Oregon State My Current Research Interests –High Frequency (> 20GHz) Serial Links –Low power (< 1Gbs/mW) signaling –High Sampling Rate (> 20GS/s), Low Resolution ADC Tsinghua Research –Low Power(< 2mW), Low Voltage(< 1V) RF Receiver –Programmable, Redundant, Self-healing RF Circuit Design with On-Die Calibration

8. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang 4Gb/s Low Power, Area Efficient Serial Links Interconnection between different chips Transmitter Equalization Receiver Offset Cancellation 2000 0.25um Testchip 2001 0.25um Testchip 4Gb/s Transmitter Output 4Gb/s Transmitter Output, 1m 4Gb/s Transmitter Output, Equalized Ming-Ju E. Lee, William J. Dally, John W. Poulton, Patrick Chiang, Stephen F. Greenwood. An 84-mW 4Gb/s Clock and Data Recovery Circuit for Serial Link Applications. VLSI Circuits Symposium, Kyoto, Japan, June 2001, pp. 149-152.An 84-mW 4Gb/s Clock and Data Recovery Circuit for Serial Link Applications. Ming-Ju E. Lee, William Dally, Patrick Chiang. Low-Power Area-Efficient High-Speed I/O Circuit Techniques. IEEE Journal of Solid-State Circuits, November 2000, Vol. 35, No. 11, pp. 1591-1599.Low-Power Area-Efficient High-Speed I/O Circuit Techniques. Transmitter Output Router Backplane(1m, FR4) Receiver Input IBM Processor

9. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang 20Gb/s 0.13um CMOS Serial Link Transmitter Jitter = 2.2ps/15.6ps RMS/pk-pk Data Rate = 19.2Gb/s Clock Recovery RX PRBS Check PRBS Gen TX DLL Test Interface 700um 1.1mm 10GHz PLL Transmitter Muxing Phase Interpolators Test Structures –165mW / transmitter – 0.23mm^2 Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh, and Mark Horowitz. A 20Gb/s 0.13um CMOS Serial Link Transmitter Using an LC-PLL to Directly Drive the Output Multiplexer. IEEE Journal of Solid-State Circuits, Vol. 40, No. 4, April 2005, pp. 1004-1011.A 20Gb/s 0.13um CMOS Serial Link Transmitter Using an LC-PLL to Directly Drive the Output Multiplexer Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh, and Mark Horowitz. A 20Gb/s 0.13um CMOS Serial Link Transmitter Using an LC-PLL to Directly Drive the Output Multiplexer. 2004 Symposium on VLSI Circuits, June 15-19, 2004, pp. 272-275.A 20Gb/s 0.13um CMOS Serial Link Transmitter Using an LC-PLL to Directly Drive the Output Multiplexer

10. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang 20Gb/s 0.13um CMOS Transceiver –361mW / transceiver – 0.46mm^2 –20mV input sensitivity 500um 600um 350um 450um Transmitter Receiver 33mV 37ps 43ps 80mV 62mV 35ps 36ps 72mV Unequalized (no channel loss) Unequalized (-6.5dB @ 10GHz) 62mV 35ps Equalized (no channel loss) Equalized (-6.5dB @ 10GHz) 2-Tap Equalization Demultiplexing Receiver

11. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang High Sampling Rate, Low Resolution A/D Converters High sampling rate, low resolution ADCs important for: –Ultrawideband RF –High speed serial links –10G Ethernet of copper State of the Art: Ken Poulton, ISSCC 2003

12. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang Proposed New ADC Modifications to thesis receiver architecture –Front-end samplers –Downstream amplifiers –Calibration circuits compensating timing offset > 10x power reduction > 10x area reduction Conventional Architecture New Architecture

13. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang Summary Overview of Oregon State My Current Research Interests –High Frequency (> 20GHz) Serial Links –Low power (< 1Gbs/mW) signaling –High Sampling Rate (> 20GS/s), Low Resolution ADC Tsinghua Research –Low Power(< 2mW), Low Voltage(< 1V) RF Receiver –Programmable, Redundant, Self-healing RF Circuit Design with On-Die Calibration

14. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang Tsinghua Research: Super-Regenerative Receiver Previous Work This Work Reduced Power Consumption vs. Conventional  High sensitivity due to Q-enhanced LC Filter

15. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang Super-Regenerative Input Sensitivity Pin = no signal Pin < -150dBm Pin < -170dBm Pin < -190dBm Oscillation Time Increasing Q Receiver Voltage Input

16. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang Summary Overview of Oregon State My Current Research Interests –High Frequency (> 20GHz) Serial Links –Low power (< 1Gbs/mW) signaling –High Sampling Rate (> 20GS/s), Low Resolution ADC Tsinghua Research(with Dr. Baoyong Chi) –Low Power(< 2mW), Low Voltage(< 1V) RF Receiver –Programmable, Redundant, Self-healing RF Circuit Design with On-Die Calibration

17. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang Low Noise Amplifier Abidi, ISSCC 2006 Analog / RF Design in Deep Submicron Transistor scaling advantages: –Ubiquitous transistors –Transistor f T –SOC Integration Disadvantages: –Process variation –Inaccurate device/parasitic modeling –Increased design time / cost –Un-optimum fabricated silicon Analog / RF Design has not changed!

18. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang Example: 2.4GHz LNA S 11, S 22 SS,TT,FF Process Skew, 30mV Threshold Variation 180nm UMC, RF/mixed-signal process Variation MUCH worse than simulated –Not including metal/dielectric variation –Not RF design in 90nm/65nm logic process

19. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang Proposing Programmable, Parallel RF Circuit Design Transistors are free Create parallel, digitally switchable RF Circuits Novelty: Digital On-Die Calibration –Exact device models / parasitic extraction unnecessary –Design time reduction –Design benefit from Deep Submicron CMOS

20. June 23, 2006 Patrick Chiang Email: pchiang@eecs.oregonstate.edu Website: eecs.oregonstate.edu/~pchiang Conclusion Oregon State is a great place to pursue a graduate degree I am looking for intense, bright students to start my research group Questions? –Email: pchiang_calstan@yahoo.com –Email: pchiang@ece.oregonstate.edu