1. Dec. 6, 2005ELEC6970-001 Glitch Power1 Low power design: Insert delays to eliminate glitches Yijing Chen Dec.6, 2005 Auburn university

2. Dec. 6, 2005ELEC6970-001 Glitch Power2 Components of Power Dynamic Signal transitions Logic activity Glitches Short-circuit Static Leakage

3. Dec. 6, 2005ELEC6970-001 Glitch Power3 Dynamic Power Each transition of a gate consumes CV2/2. Methods of power saving: Minimize load capacitances Transistor sizing Library-based gate selection Reduce transitions Logic design Glitch reduction

4. Dec. 6, 2005ELEC6970-001 Glitch Power4 Glitch Power Reduction Design a digital circuit for minimum transient energy consumption by eliminating hazards

5. Dec. 6, 2005ELEC6970-001 Glitch Power5 Theorem For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition. Output logic state changes One transition is necessary Output logic state unchanged No transition is necessary

6. Dec. 6, 2005ELEC6970-001 Glitch Power6 Balanced Delay Method All input events arrive simultaneously Overall circuit delay not increased Delay buffers may have to be inserted 1 1 1 1 1 1 1 1 3 1 1 4?

7. Dec. 6, 2005ELEC6970-001 Glitch Power7 Cell of multiplier Static power: 320.0184pW Average power: 107.1806uW

8. Dec. 6, 2005ELEC6970-001 Glitch Power8 Simulation result of cell

9. Dec. 6, 2005ELEC6970-001 Glitch Power9 Delay is added in the cell

10. Dec. 6, 2005ELEC6970-001 Glitch Power10 Simulation result for delay is added Static power: 568.6279pW average power: 144.8164uW

11. Dec. 6, 2005ELEC6970-001 Glitch Power11 4x4 multiplier

12. Dec. 6, 2005ELEC6970-001 Glitch Power12 4x4 multiplier simulation result Static power: 4.7694nW, average power:1.8339mW

13. Dec. 6, 2005ELEC6970-001 Glitch Power13 Critical path i j Cell Mij has the longest delay path length of 2i+j+1

14. Dec. 6, 2005ELEC6970-001 Glitch Power14 Delay balanced multiplier cell

15. Dec. 6, 2005ELEC6970-001 Glitch Power15 Modified 4X4 multiplier

16. Dec. 6, 2005ELEC6970-001 Glitch Power16 Conclusion The delay-balancing technique can be used on all types of parallel array multipliers such as Booth ’ s multiplier and Wallace Tree multiplier. Achieves power reduction of 36% on a parallel array multiplier

17. Dec. 6, 2005ELEC6970-001 Glitch Power17 Reference Dr. AGRAWAL ’ s Elec 6970 slides Gary Yeap (motorola), Practical low power digital VLSI design, Kiuwer Academic publishers, 1998.