1. Interconnect Verification 1 Outline –What is Interconnect Verification? –Why Interconnect Verification? –Interconnect Verification Algorithms Goal –Understand IV problem –Understand IV algorithms

2. What is Interconnect Verification? Netlist comparison –Are two netlists equivalent? –If not, where are they different? »useless without this –Sometimes called layout vs. schematic (LVS) Goals –determine if layout implements schematic –map layout to schematic for back-annotation Approach –graph isomorphism 4/2 Circuit Extractor Interconnect Verification Extracted Netlist Equality, Differences

3. Why Interconnect Verification? Schematic --> layout an imperfect process –bugs in layout synthesis tools –hand design Schematic --> layout transformations –swap gate inputs –AND-OR => NAND-NAND structures Back-annotation –user may not label all nets –map geometry at (x,y) to net in schematic –e.g. insert extracted parasitic into schematic A B B A vs. 4/2

4. Interconnect Verification Algorithms Convert netlist to graph –device nodes »type, terminal labels »attributes, e.g. size –net nodes –bipartite graph »edges only between device and net nodes Perform graph isomorphism test –given graphs G 1 and G 2 –is there a 1:1 function f »mapping vertices of G 1 onto vertices of G 2 »such that x and y are adjacent in G 1 (connected by an edge) iff f(x) and f(y) are adjacent in G 2 DD EE x x g x x g x x g x x g

5. Graph Isomorphism Partitioning algorithm –compute vertex invariants or color »function of vertex properties - labels, degree, etc. »function of neighboring vertices - type, color, equivalence class –partition vertices by color into equivalence classes –recolor based on new neighboring classes –repeat until single vertex in each class or no progress –sort each graph by vertex color and compare lists Time Complexity –unknown in general case (NP-Intermediate) –known algorithms are exponential in worst case –partitioning is O(V) in practice »if graphs are equivalent and unambiguous

6. Partitioning Algorithm for G in G1...G2 do { do { for i = 0...V do { G.vertex[i].color = VertexColor(G.vertex[i]) AddToClass(G.vertex[i].color, G.vertex[i]) } } until all vertex[i].color are unique or no progress SortByColor(G) } for i = 0...V do { if G1.vertex[i].color != G2.vertex[i].color report error }

7. Partitioning Algorithm AddToClass(color, vertex) { append(class[color],vertex) vertex.class = class[color] } VertexColor(vertex) { compute color from vertex properties current vertex color, neighboring vertex colors }

8. Example a a a c b ba a: 3 edges b: 4 edges c: 2 edges a3 a1 c b1 b2a2 a1: a,b,c a2: a,b,b a3: a,a,b b1: a,a,b,c b2: a,a,a,b a3a a3b a1 c b1 b2a2 a3a: a1,a3,b2 a3b: a3,a2,b2 c

9. GEMINI Example DD EE x x g x x g x x g x x g DD EE x x g x x g x x g x x g N2 N4 N2 DD DE DD EE x x g x x g x x g x x g (N2 (x: DD DD)) (DD (g: N2) (x: N2 N2)) (N2 (x: DD DE)) (DE (g: N4 (x: N2 N2)) (DD (g: N4) (x: N2 N4)) (N2 (g: DD DE)) (DE (g: N2) (x: N2 N4)) (N2 (x: DE DE))

10. CMOS Example P P NN x x g x x g x x g x x g P P NN x x g x x g x x g x x g N2xN NxP NgPgNNxP2xN NgPgN N2xP DP DN NxP create graph color devices by type color nets by adjacent device, terminal type

11. CMOS Example P P NN x x g x x g x x g x x g N2xN NxP NgPgNNxP2xN NgPgN N2xP DPgPgNxP2xP DPgPgN2xPxP2xN DNgPgN2xNxP2xN P P NN x x g x x g x x g x x g N2xN NxP NgP2gNNxP2xN NgP1gN N2xP DPgPgNxP2xP (P1) DPgPgN2xPxP2xN (P2) DNgP1gN2xNxP2xN DNgP2gN2xNxP2xN DNgPgN2xNxP2xN color devices by adjacent nets color nets by adjacent devices color devices by adjacent nets all vertices uniquely colored

12. Coloring Functions Hashing –color i+1 = f(color i, g(color neighbor1, edge-class neighbor1 ), g(color neighbor2, edge-class neighbor2 ),...) –edge class - e.g. source, drain, gate –g - source and drain are equivalent –hash to get compact colors - color is an integer Signatures –s next = s current + c sd s source + c sd s drain + c g s gate –s - signature –c - weights to treat transistor terminals differently –snet next = snet current + w i s device i + w j s device j +... –w - weights for terminal types

13. Coloring Function Issues Speed –recoloring is main computation »want to be fast –ideally look only at attributes of vertex, adjacent vertices –can initially look at very few attributes »only look at more if recoloring stops Good Hash Function –hash/signature collisions slow down convergence »mistakenly give two vertices the same color »later have to detect they are really different –iterations must continue until all vertices are uniquely colored Compromise between the two

14. Refinements Recolor only on frontier –only color vertices adjacent to singleton classes »likely to provide most useful coloring »singleton classes will not be recolored –only color vertices adjacent to recolored vertices »only these vertices can change color Speed –2-10X speedup –recolor each vertex ~2 times –speed limited by netlist I/O A B B B B B A B B B B C

15. Ambiguous Circuits Automorphism detection –Matching non-unique G 1 and G 2 classes cannot be subdivided –causes »invariant not sufficiently powerful - unlikely in real circuits »circuit is automorphism - ring oscillator, logic equivalence –force vertex in G 1 and G 2 to be equivalent and continue »may have to backtrack »require user to add labels ABCabc Legal mappings: {A,a} (B,b} {C,c} {A,b} {B,c} {C,a} {A,c} {B,a} {C,b} vs. A B B A

16. Finding Circuit Errors Example –Vdd connection missing from pullup transistor –result - Vdd vertices are colored differently in G 1 and G 2 »different degree => different color –color difference rapidly propagated to all vertices –no vertex colors match, no useful diagnostic Solution –label classes that do not have corresponding class in other graph as suspect »corresponding = same vertex count, same color –remove suspect vertices from class refinement process »do not use when recoloring other vertices –when no further recoloring possible, examine suspects –differences will be isolated to suspect classes »e.g. difference in Vdd net, pullup transistor