1. Binary Counters Lecture L8.3 Section 8.2

2. Counters 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter

3. CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter

4. s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter Q2 Q1 Q0 00011110 0 1 11 1 1 Q2.D Q2.D = !Q2 & Q1 & Q0 # Q2 & !Q1 # Q2 & !Q0

5. s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter Q2 Q1 Q0 00011110 0 1 1 1 1 1 Q1.D Q1.D = !Q1 & Q0 # Q1 & !Q0

6. s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D Divide-by-8 Counter Q2 Q1 Q0 00011110 0 1 1 1 1 1 Q0.D Q0.D = ! Q0

7. div8cnt.abl MODULE div8cnt TITLE 'Divide by 8 Counter' DECLARATIONS hex7seg interface([D3..D0] -> [a,b,c,d,e,f,g]); d7R FUNCTIONAL_BLOCK hex7seg; " INPUT PINS " CLK PIN 12; " 1 Hz clock (jumper) clear PIN 11;" switch 1 " OUTPUT PINS " Q2..Q0 PIN 41,43,44 ISTYPE 'reg'; " LED 14..16 Q = [Q2..Q0]; " 3-bit output vector [a,b,c,d,e,f,g] PIN 15,18,23,21,19,14,17 ISTYPE 'com'; " Rightmost (units) 7-segment LED display

8. EQUATIONS Q.AR = clear; Q.C = CLK; Q2.D = !Q2 & Q1 & Q0 # Q2 & !Q1 # Q2 & !Q0; Q1.D = !Q1 & Q0 # Q1 & !Q0; Q0.D = !Q0; [a,b,c,d,e,f,g] = d7R.[a,b,c,d,e,f,g]; d7R.[D2..D0] = Q; d7R.D3 = 0; div8cnt.abl (cont’d) Clock Async clear

9. test_vectors(CLK -> Q).C. -> 1;.C. -> 2;.C. -> 3;.C. -> 4;.C. -> 5;.C. -> 6;.C. -> 7;.C. -> 0;.C. -> 1;.C. -> 2;.C. -> 3;.C. -> 4; END div8cnt.abl (cont’d)

10. div8cnt Simulation

11. Counters 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter

12. CLK DQ !Q CLK DQ !Q CLK DQ !Q Q0Q0.D Q1 Q2 Q1.D Q2.D s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D 3-Bit Down Counter

13. Q2 Q1 Q0 00011110 0 1 11 1 1 Q2.D Q2.D = !Q2 & !Q1 & !Q0 # Q2 & Q1 # Q2 & Q0 s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D

14. 3-Bit Down Counter Q2 Q1 Q0 00011110 0 1 1 1 1 1 Q1.D Q1.D = !Q1 & !Q0 # Q1 & Q0 s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D

15. 3-Bit Down Counter Q2 Q1 Q0 00011110 0 1 1 1 1 1 Q0.D Q0.D = ! Q0 s0 0 0 0 1 1 1 s1 0 0 1 0 0 0 s2 0 1 0 0 0 1 s3 0 1 1 0 1 0 s4 1 0 0 0 1 1 s5 1 0 1 1 0 0 s6 1 1 0 1 0 1 s7 1 1 1 1 1 0 State Q2 Q1 Q0 Q2.D Q1.D Q0.D

16. Counters 3-Bit Up Counter 3-Bit Down Counter Up-Down Counter

17. Up-Down Counter Q0 Q1 Q2 clock UD UD = 0: count up UD = 1: count down

18. Up-Down Counter 1 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 1 0 0 0 1 1 0 1 1 0 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 1 1 0 UD Q2 Q1 Q0 Q2.D Q1.D Q0.D 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 0 0 UD Q2 Q1 Q0 Q2.D Q1.D Q0.D Up-CounterDown-Counter

19. UD Q2 Q1 Q0 00011110 00 01 11 10 Up-Down Counter Make Karnaugh maps for Q2.D, Q1.D, and Q0.D