1. 4/28/05 Raghuraman: ELEC7250 1 To Generate a Single Test Vector to detect all/most number of faults in a given set Project by: Arvind Raghuraman Course Project ELEC 7250

2. 4/28/05Raghuraman: ELEC72502 Problem Statement The Objective of the project is to determine a test vector that could detect all/most number of faults in a given set. The Objective of the project is to determine a test vector that could detect all/most number of faults in a given set. As a suggested improvement investigation was done on extending the algorithm developed for test set compaction. As a suggested improvement investigation was done on extending the algorithm developed for test set compaction.

3. 4/28/05Raghuraman: ELEC72503 Background work Major Combinational ATPG Algorithms: D-Algorithm (Roth) -- 1966D-Algorithm (Roth) -- 1966 PODEM (Goel) – 1981PODEM (Goel) – 1981 Advanced ATPG Algorithms: FAN – Multiple Backtrace (1983) FAN – Multiple Backtrace (1983) TOPS – Dominators (1987) TOPS – Dominators (1987) SOCRATES – Learning (1988) SOCRATES – Learning (1988) Legal Assignments (1990) Legal Assignments (1990) EST – Search space learning (1991) EST – Search space learning (1991) BDD Test generation (1991) BDD Test generation (1991) Implication Graphs and Transitive Closure (1988 - 97) Implication Graphs and Transitive Closure (1988 - 97) Recursive Learning (1995) Recursive Learning (1995)

4. 4/28/05Raghuraman: ELEC72504 ATPG / Vector Detection Algorithm Combinational circuitATALANTA ATPG SET – F n {TF n1, TF n2,....TF nm } F1 - > (TFn1) = {TV1,TV4,TV6} F2 - > (TFn2) = {TV7, TV8,TV6,TV1} F3- > (TFn3) = {TV27, TV5,TV6,TV13} …….. TFnm Output From ATALANTA ATPG Equivalence Collapsing and ATPG Bench file for the given combinational circuit SET - TVFn = {TVFn1, TVFn2,....TVFnm} TV1 - > (TVFn1) = {f1,f4,f6} TV2 - > (TVFn2) = {f7,f8,f6,f1} TV3- > (TVFn3) = {f27,f5,f6,f13} …….. TVFnm Set Manipulation R = MAXIMUM Set Size (SET - TVFnm)  TVx Test Vector TVx Detects the most / All Faults in the given combinational Circuit

5. 4/28/05Raghuraman: ELEC72505 Snap Shot of the application

6. 4/28/05Raghuraman: ELEC72506 Suggested Improvements Test Compaction strategy: The vector The vector TVx and the faults detected by the vector are dropped from the parent lists. Now by rerunning the same algorithm we get another vector that detects the most number of faults. Repeat step 1. By repeating the process and by keeping track of the fault coverage after every iteration we can obtain a compact test set with required fault coverage.

7. 4/28/05Raghuraman: ELEC72507 Results Circuit under Test : c17.bench combinational circuit Number of test patterns : 54 Number of test patterns : 54 Fault coverage : 100.000 % Fault coverage : 100.000 % Number of collapsed faults : 22 Number of collapsed faults : 22 Application output Test Vector " 000xx " detects 1 faults Test Vector " 001xx " detects 1 faults Test Vector " 00xxx " detects 2 faults Test Vector " 010xx " detects 3 faults Test Vector " 0110x " detects 5 faults Test Vector " 0111x " detects 3 faults Test Vector " 100xx " detects 4 faults Test Vector " 10111 " detects 1 faults Test Vector " 101x0 " detects 1 faults Test Vector " 101xx " detects 2 faults Test Vector " 110xx " detects 3 faults Test Vector " 11100 " detects 2 faults Test Vector " 11101 " detects 1 faults Test Vector " 11110 " detects 1 faults Test Vector " 11111 " detects 1 faults Test Vector " 1111x " detects 2 faults Test Vector " 1x1xx " detects 1 faults Test Vector " x0011 " detects 1 faults Test Vector " x00x0 " detects 1 faults Test Vector " x00x1 " detects 3 faults Test Vector " x0101 " detects 3 faults Test Vector " x0111 " detects 2 faults Test Vector " x0xx0 " detects 1 faults Test Vector " x101x " detects 1 faults Test Vector " x10x0 " detects 1 faults Test Vector " x10xx " detects 2 faults Test Vector " x1100 " detects 1 faults Test Vector " x110x " detects 1 faults Test Vector " x111x " detects 2 faults Test Vector " xx111 " detects 1 faults Application Result Test Vector " 0110x " detects 5 faults

8. 4/28/05Raghuraman: ELEC72508 Conclusion The Application developed correctly identifies the test vector of interest. The Application developed correctly identifies the test vector of interest. The proposed strategy for test compaction should be tested on other circuits and its performance should be ascertained. The proposed strategy for test compaction should be tested on other circuits and its performance should be ascertained. The Application can be used as a Generic Tool for any combinational circuits, it can directly accept the output file from ATALANTA and generate the test vector of interest. The Application can be used as a Generic Tool for any combinational circuits, it can directly accept the output file from ATALANTA and generate the test vector of interest.

9. 4/28/05Raghuraman: ELEC72509 References Class Lecture Notes ELEC 7250 Class Lecture Notes ELEC 7250 Essentials of Electronic Testing, Michael L.Bushnell, Vishwani D.Agarwal Essentials of Electronic Testing, Michael L.Bushnell, Vishwani D.Agarwal