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Recitation 8 (Nov. 1) Outline Lab 5 hints Virtual Memory Reminder Shell Lab: Due THIS Thursday TA: Kun Gao Modified from Minglong Shao’s Recitation, Fall 2004
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Lab 5 A tiny shell (tsh) with job control & I/O redirection Key points: Understand process tree Executing programs Reap all child processes Handle SIGCHLD, SIGTSTP, SIGINT Avoid race hazard I/O redirection
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Process tree for shell Fore- ground job Back- ground job #1 Back- ground job #2 Shell Child pid=10 pgid=10 Foreground process group 20 Background process group 32 Backgroud process group 40 pid=20 pgid=20 pid=32 pgid=32 pid=40 pgid=40 pid=21 pgid=20 pid=22 pgid=20 Each job has a unique process group id int setpgid(pid_t pid, pid_t pgid); setpgid(0, 0);
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Process tree for shell (part 2) Fore- ground job Back- ground job #1 Back- ground job #2 tsh Child pid=10 pgid=10 Foreground process group 20 Background process group 32 Backgroud process group 40 pid=20 pgid=20 pid=32 pgid=32 pid=40 pgid=40 pid=21 pgid=20 pid=22 pgid=20 UNIX shell pid=5 pgid=5 Foreground job receives SIGINT, SIGTSTP, when you type ctrl-c, ctrl-z Forward signals int kill(pid_t pid, int sig) pid > 0: send sig to specified process pid = 0: send sig to all processes in same group pid < -1: send sig to group -pid
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Execute program int execve(const char *fname, char *const argv[], char *const envp[]); Examples: execve(“/bin/ls”, NULL, NULL); execve(“./mytest”, argv, envp);
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Reaping child process waitpid(pid_t pid, int *status, int options) pid: wait for child process with pid (process id or group id) -1: wait for any child process status: tell why child terminated options: WNOHANG: return immediately if no children zombied WUNTRACED: report status of terminated or stopped children In Lab 5, use waitpid(-1, &status, WNOHANG|WUNTRACED) In sigchld_handler() : while ((c_pid = waitpid(…)) > 0) { … }
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Reaping child process (part 2) int status; waitpid(pid, &status, WNOHANG|WUNTRACED) What to check in sigchld_handler: WIFEXITED(status): child exited normally (the child finished, and quit normally on its own) WEXITSTATUS(status): returns code when child exits WIFSIGNALED(status): child exited because a signal is not caught (SIGINT, or typing CTRL-C) WTERMSIG(status): gives the terminating signal number WIFSTOPPED(status): child is stopped by the receipt of a signal (SIGSTOP, or typing CTRL-Z) WSTOPSIG(status): gives the stop signal number
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Reaping child process (part 3) Where to put waitpid(…) In sigchld_handler() : for both tsh should still wait for fg job to complete, how?
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Busy wait for foreground job In eval() : if(fork() != 0) { /* parent */ addjob(…); while(fg process still alive){ /* do nothing */ }
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Sleep In eval() : if(fork() != 0) { /* parent */ addjob(…); while(fg process still alive){ sleep(1); }
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Race hazard A data structure is shared by two pieces of code that can run concurrently Different behaviors of program depending upon how the schedule interleaves the execution of code.
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An example of race hazard sigchld_handler() { while ((pid = waitpid(…)) > 0){ deletejob(pid); } eval() { pid = fork(); if(pid == 0) { /* child */ execve(…); } /* parent */ /* signal handler may run BEFORE addjob()*/ addjob(…); }
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An okay schedule Shell Signal HandlerChild fork() addjob() execve() exit() sigchld_handler() deletejobs() time
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A problematic schedule Shell Signal HandlerChild fork() execve() exit() sigchld_handler() deletejobs() time addjob() Job added to job list after the signal handler tried to delete it!
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Solution: blocking signals sigchld_handler() { pid = waitpid(…); deletejob(pid); } eval() { sigprocmask(SIG_BLOCK, …) pid = fork(); if(pid == 0) { /* child */ sigprocmask(SIG_UNBLOCK, …) execve(…); } /* parent */ /* signal handler might run BEFORE addjob() */ addjob(…); sigprocmask(SIG_UNBLOCK, …) }
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Solution: blocking signals (part 2) What should our block set be? SIGSTP SIGINT SIGCHLD
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I/O redirection Do it before call execve() in child process eval() { pid = fork(); if(pid == 0) { /* child */ /* Redirect I/O */ if (redirect_input) dup2(…);/* redirect STDIN */ if (redirect_output) dup2(…);/* redirect STDOUT */ execve(…); } addjob(…); }
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dup2(int oldfd, int newfd) Covered in Chapter 11 oldfd : old file descriptor newfd : new file descriptor Dup2 makes newfd be a copy of the oldfd (i.e. operations on newfd is done on oldfd instead) Some examples: Get input from in_fd instead of standard input dup2(in_fd, STDIN_FILENO); Print output to out_fd instead of standard output dup2(out_fd, STDOUT_FILENO);
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Reminders Some important system calls: fork(), execve(), waitpid(), sigprocmask(), setpgid(), kill() … Check man pages for details about system calls man 2 kill Check return values of all system calls STEP by STEP Test your shell by typing commands first Each trace worth the same (work on easy ones first!) Start now!
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Virtual memory One of the most important concepts in CS Why use virtual memory (VM) Use RAM as a cache for disk Easier memory management Access protection Enable “partial swapping” Share memory efficiently
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Virtual memory CPU 0: 1: N-1: Memory 0: 1: P-1: Page Table Disk Virtual Addresses Physical Addresses Page Page table Page hits, Page faults Demand Paging Per Process:
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Conceptual address translation Higher bits of address (page number) mapped from virtual addr. to physical addr. Lower bits (page offset) stay the same. virtual page number (VPN)page offset virtual address physical page number (PPN) page offset physical address 0p–1 address translation pm–1 n–1 0p–1p Virtual Memory: up to 2 n -1 bytes Physical Memory: up to 2 m -1 bytes
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Address translation through page table Translation Separate (set of) page table(s) per process VPN forms index into page table (points to a page table entry)
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Address translation with TLB virtual address virtual page numberpage offset physical address n–10p–1p validphysical page numbertag validtagdata = cache hit tagbyte offset index = TLB hit TLB Cache...
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Integrating VM and cache Most caches are physically addressed Why? Perform address translation before cache lookup, could potentially go to memory =*( TLB keeps things manageable TLB Cache/Memory 1. VA4. PA MMU/ Translation 2. VPN3. PTE 5. Data CPU
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Integrating VM and cache (TLB hit) Most caches are physically addressed Why? Perform address translation before cache lookup, could potentially go to memory =*( TLB keeps things manageable TLB Cache/Memory 1. VA4. PA MMU/ Translation 2. VPN3. PTE 5. Data CPU
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Integrating VM and cache (TLB miss) TLB miss, but page table is in cache/memory TLB Cache/Memory 1. VA 3. PTEA (PTBP + VPN) MMU/ Translation 2. VPN 6. Data CPU 4. PTE 5. PA
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What is the worst case mem read (most delay)? TLB miss, page fault on page table, then page fault on memory read TLB Cache/Memory 1. VA 3. PTEA (PTBP + VPN) MMU/ Translation 2. VPN 6. Data CPU 4. PTE 5. PA DISK Page Fault/ Page Table Page Fault/ Mem Read
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Example Understand end-to-end addr. translation 20-bit virtual addresses 18-bit physical addresses Page size is 1024 bytes TLB is 2-way associative with 16 total entries
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Part 1 A. Virtual address B. Physical address 161514131211109876543171821019 VPN VPO TLBTTLBI 16151413121110987654317210 PPN PPO
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Example: TLB and page table
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Part 2 Virtual address 0x04AA4 A. 04AA4 = 0000 0100 1010 1010 0100 B. Address translation C. Physical address 01 1010 0010 1010 0100 parameterValueParameterValue VPN0x012TLB hit?Y TLB Index0x2Page fault?N TLB Tag0x02PPN0x68
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Part 2 Virtual address 0x78E6 A. 078E6 = B. Address translation C. Physical address parameterValueParameterValue VPN0x01ETLB hit?N TLB Index0x6Page fault?N TLB Tag0x03PPN0x57 0000 0111 1000 1110 0110 01 0101 1100 1110 0110
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End-to-end address translation Section 10.6.4: a concrete example Read carefully and solve practice problem 10.4
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