1. Designing the 8086/8088 Microcomputer System

2. Typical Microprocessor Based System
Control
Memory/IO
CPU
Address
Data

3. 8086/8088 Busses Address Bus Data Bus Control Bus
20 address lines so a 220 byte address space.
Pins A0-A19 provide the address
For 8086, A0-A15 are multiplexed with D0-D15 to form AD0-AD15
For 8088, A0-A7 are multiplexed with D0-D7 to form AD0-AD7
Data Bus
For 8086, 16 bit data bus D0-D15 (multiplexed as AD0-AD15)
For 8088, 8 bit data bus D0-D7 (multiplexed as AD0-AD7)
Control Bus
For memory access, the following pins are used:
RD’, WR’, M/IO’, DT/R’, DEN’, ALE, BHE’
Other input signals to control 8086 performance:
clk ,reset , ready , hold , test’, intr , nmi ,mn’/mx
- The intr and hold are acknowledged through intra and holda respectively.

4. 8086/8088 Pin Configuration

5. 8086 Control Pins

6. 8284A

8. Clock Generator

9. Ready logic (adding wait states)

13. 8086/8088 Detailed Memory Interface
CS’,WE’,OE’
Control
Control
MEMORY
Address Decoding
Unique per device
Latches
Buffers
Demultiplexing
8086/8
Partial
Address
Address
Multiplexed
Addr/Data
Data

14. 8088 Bus Structure

16. 8086 maximum & minimum modes
The mode is controlled by MN/MX.
Maximum mode is obtained by connecting MN/MX to high and minimum mode is by connecting it to high.
Having two different modes (minimum and maximum) is used only 8088/8086.
Each mode enables a different control structure.
Minimum mode operation and control signals are very similar to those of 8085.
So bit peripherals can be used with 8086 without special considerations.
Easy and least expensive way to build single processor systems

17. 8086/8088 Pin Configuration Differences

18. Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system.
All the control signals (except RD ) are not generated by the microprocessor.
But we still need those control signals.
Solution:
8288.

20. 0 1 0 Write I/O port IOWC, AIOWC 0 1 1 Halt none
S2 S1 S operation signal
Interrupt Acknowledge INTA
Read I/O port IORC
Write I/O port IOWC, AIOWC
Halt none
Instruction Fetch MRDC
Read Memory MRDC
Write Memory MWTC, AMWC
Passive none

21. QS1 QS0
No instruction taken from queue.
First byte of current instruction taken from queue.
Queue flushed.
Byte other than first byte taken from queue.