2. High speed digital systems laboratory Part A - Presentation Project Name: Serial Communication Analyzer Presenter Name: Igal Kogan Alexander Rekhelis Instructor: Hen Broodney Semester: Winter-Spring 2001/2

3. High speed digital systems laboratory Project Goals Implementation of testing and debugging device for serial communication protocol RS-232 and DSP protocol McBSP. Both protocols are encoded and/or decoded by Altera FPGA. Also PCI Interface protocol, that implemented in PCI MegaCore, is managed by Altera FPGA. The design will base on Altera Flex PCI Development Kit and the external devices will connect through bridges that are specially designed as RS-232 and McBSP protocols buffers.

4. High speed digital systems laboratory Abstract The device will manage the data in several ways: 1) As data buffer it will transfer the data from the input device to the output device. 2) As communication analyzer it will read the data from input, send it to PC through PCI Bus for processing, and according to user commands will send the updated data to output. Note: Since the communication is bi-directional, input and output devices can be switched constantly.

5. High speed digital systems laboratory Abstract (cont.) RS-232 McBSP Serial Communication Analyzer

6. High speed digital systems laboratory Highlights of RS232 protocol RS-232 is an electrical interface standard between Data Terminal Equipment (DTE) and Data Circuit-Terminating Equipment (DCE) such as modems, PALM, mouse and so. RS-232 is used for asynchronous data transfer as well as synchronous links.asynchronous It appears under different incarnations such as RS-232C, RS-232D, V.24, V.28 or V.10 but essentially all these interfaces are interoperable.

7. High speed digital systems laboratory PC Com Port - EIA-574 RS-232 pin out DB-9 pin used for Asynchronous Data

8. High speed digital systems laboratory One byte of asynchronous data

9. High speed digital systems laboratory Highlights of McBSP protocol –Full-duplex communication –Double-buffered data registers, which allow a continuous data stream –Independent framing and clocking for receive and transmit –Direct interface to industry-standard analog interface chips (AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices –External shift clock or an internal, programmable frequency shift clock for data transfer –Autobuffering capability through the 5-channel DMA controller.

10. High speed digital systems laboratory McBSP Interface Signals PinI/O/Z † Description CLKRI/O/ZReceive clock CLKXI/O/ZTransmit clock CLKSIExternal clock DR IReceived serial data DX O/ZTransmitted serial data FSRI/O/ZReceive frame synchronization FSXI/O/ZTransmit frame synchronization

11. High speed digital systems laboratory PCI Bus Local Bus חלוקת ה -PCI Core ליחידות לוגיות, כפי שמומש ע ” י חברת Altera. תפקידו למנשק בין ה -PCI Bus לבין Control Logic Block. PCI Core PCI Core

12. High speed digital systems laboratory Software (Hardware) We are currently focused on RS232 protocol implementation. The communication can be handled at: 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 baud rate. The communication rate, condition (with or without handshake) analyzing and test options will be determined by the GUI through the WinDriver. Control Logic block will provide the proper interactions between PCI Core and RS232 or McBSP communication blocks (by local bus).

13. High speed digital systems laboratory Hardware All hardware will be implemented on Altera FLEX PCI Development Kit. One channel for RS-232 communication is already placed on the kit. The implementation of the second RS-232 communication channel that connects to the Altera on the kit and also the implementation of the connections between two McBSP channels on DSP board to the Altera on the kit board are currently in progress.

14. High speed digital systems laboratory Altera PCI Development Board

15. High speed digital systems laboratory Technical Specification 1) Interface voltages: 1.1) RS-232 – ‘0’ -> +3v : +15v ‘1’ -> -3v : -15v 1.2) McBSP – ‘0’ -> 0v ‘1’ -> +3.3v 2) Distances – 0m : 2m 3) Communication rates : 3.1) RS-232 – 1200,2400,4800,9600,19200,38400,57600,115200 3.2) McBSP – 33Mbps (pci bus clock)

16. High speed digital systems laboratory Technical Specification (cont.) 4) RS-232 interface working with handshake or without handshake. 5) Loopback connectivity test. 6) Communication reliability tests: 6.1) Parity checks. 6.2) CRC tests without acknowledge. 6.3) CRC tests with acknowledge.

17. High speed digital systems laboratory RS-232 pin out (addition)

18. High speed digital systems laboratory McBSP pin out (addition)

19. High speed digital systems laboratory System Block Diagram Altera Flex PCI Development Kit PCI RS-232 Communication Device McBSP Communication Device RS-232 Communication Device McBSP Communication Device WinDriver GUI

20. High speed digital systems laboratory System modules diagram (FPGA) RS-232 Protocol RS-232 Protocol McBSP Protocol McBSP Protocol Control Logic PCI MegaCore

21. High speed digital systems laboratory FPGA block diagram

22. High speed digital systems laboratory FPGA block diagram

23. High speed digital systems laboratory FPGA block diagram

24. High speed digital systems laboratory FPGA block diagram

25. High speed digital systems laboratory RS-232 simulation

26. Design with HDL Designer Simulation with Modelsim Synthesis with Leonardo Spectrum P & R with MaxPlusII Hardware Development Tools High speed digital systems laboratory

27. R E L I A B I L I T Y T E S T S

28. High speed digital systems laboratory Reliability Tests 1) Checking our side – this is check for our hardware Serial Communication Analyzer Local loopback for all interfaces

29. High speed digital systems laboratory Example – RS-232 loopback connections

30. High speed digital systems laboratory Example – McBSP loopback connections clkx clkr dx dr fsx fsr Loopback connection

31. High speed digital systems laboratory Reliability Tests (cont.) 2) Communication device closing loopback – this test checking all hardware. Serial Communication Analyzer Communication Device

32. High speed digital systems laboratory Reliability Tests (cont.) 3) Analyzer closing loopback – this is good visual test for all our design. Serial Communication Analyzer Communication Device DataSampled Data ? ==

33. High speed digital systems laboratory Reliability Tests (cont.) 4) Parity check. Serial Communication Analyzer Communication Device G U I The GUI display the percentage of the success

34. High speed digital systems laboratory Reliability Tests (cont.) 5) CRC – Cyclic Redundancy Check (without ack) Serial Communication Analyzer Communication Device G U I The frame consist of the 10 bytes of data and 1 byte of the CRC result (sum of bits).

35. High speed digital systems laboratory Reliability Tests (cont.) 6) CRC – Cyclic Redundancy Check (with ack) Serial Communication Analyzer Communication Device G U I

36. High speed digital systems laboratory Reliability Tests (cont.) 6) CRC – Cyclic Redundancy Check (with ack) 10 bytes1 byte + + D A T AC R CA C K a)CRC – sum of the data bits from communication device b)ACK – sum of the data bits that analyzer send

37. High speed digital systems laboratory Testing of the protocols (RS-232) TerminalOur side GUI Palm Example

38. High speed digital systems laboratory Project status הכרת ה -PCI Core, שילובו בתכנון ומימוש ממשק חומרה בינו ובין יתר יחידות התכנון. לימוד ממשקי התקשורת RS-232 ו - McBSP. מימוש פרוטוקול RS232 ב -VHDL. לימוד הנושא תקשורת אמינה והגדרת כל הבדיקות שיבדקו בתקשורת.

39. High speed digital systems laboratory Part B goals מימוש פרוטוקול McBSP ב -VHDL וחיבורו ל - PCI Core. כתיבת GUI, הגדרה ומימוש ממשק למשתמש לצורך הפעלת Windows ל- Driver הכרטיס. הפעלה מלאה של נתח תקשורת טורית, ביצוע בדיקות תקינות תקשורת על ההתקנים שתומכין בפרוטוקולים נבדקים, כתיבת חוברת הדרכה למשתמש.

40. High speed digital systems laboratory Schedule Phase1 – Hardware Design Phase2 – Software Design Phase3 – Debug OctNovDecJanFebMarAprMayJunJul Phase 1 Phase 2 Phase 3

41. High speed digital systems laboratory Schedule (cont.) לוח זמנים: 04/2002 – 06/2002 : בדיקת ביצועי של הפרוטוקולים 11/04/2002 - הצגת דו"ח סופי חלק א'. 22/04/2002 - הלבשת כל מערכת תקשורת על PCIcore. 10/05/2002 - Debugging. 01/06/2002 - כתיבת GUI בעזרת WinDriver. 01/07/2002 - בדיקות אחרונות. 07/2002 : בחינות סוף סמסטר. 08/2002 : הצגת חלק ב' - הצגת כרטיס עובד על פי כל הדרישות

42. High speed digital systems laboratory תודה רבה Serial Communication Analyzer