1. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 11 Lecture 1 Introduction n VLSI realization process n Verification and test n Ideal and real tests n Costs of testing n Roles of testing n A modern VLSI device - system-on-a-chip n Course outline Part I: Introduction to testing Part II: Test methods Part III: Design for testability

2. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 12 VLSI Realization Process Determine requirements Write specifications Design synthesis and Verification Fabrication Manufacturing test Chips to customer Customer’s need Test development

3. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 13 Definitions n Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. n Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. n Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.

4. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 14 Verification vs. Test n Verifies correctness of design. n Performed by simulation, hardware emulation, or formal methods. n Performed once prior to manufacturing. n Responsible for quality of design. n Verifies correctness of manufactured hardware. n Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware n Test application performed on every manufactured device. n Responsible for quality of devices.

5. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 15 Problems of Ideal Tests n Ideal tests detect all defects produced in the manufacturing process. n Ideal tests pass all functionally good devices. n Very large numbers and varieties of possible defects need to be tested. n Difficult to generate tests for some real defects. Defect-oriented testing is an open problem.

6. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 16 Real Tests n Based on analyzable fault models, which may not map on real defects. n Incomplete coverage of modeled faults due to high complexity. n Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. n Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.

7. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 17 Testing as Filter Process Fabricated chips Good chips Defective chips Prob(good) = y Prob(bad) = 1- y Prob(pass test) = high Prob(fail test) = high Prob(fail test) = low Prob(pass test) = low Mostly good chips Mostly bad chips

8. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 18 Costs of Testing n Design for testability (DFT) Chip area overhead and yield reduction Performance overhead n Software processes of test Test generation and fault simulation Test programming and debugging n Manufacturing test Automatic test equipment (ATE) capital cost Test center operational cost

9. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 19 Design for Testability (DFT) DFT refers to hardware design styles or added hardware that reduces test generation complexity. Motivation: Test generation complexity increases exponentially with the size of the circuit. Logic block A Logic block B PI PO Test input Test output Int. bus Example: Test hardware applies tests to blocks A and B and to internal bus; avoids test generation for combined A and B blocks.

10. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 110 Present and Future* Transistors/sq. cm 4 - 10M 18 - 39M Pin count 100 - 900 160 - 1475 Clock rate (MHz) 200 - 730 530 - 1100 Power (Watts) 1.2 - 61 2 - 96 Feature size (micron) 0.25 - 0.15 0.13 - 0.10 1997 -20012003 - 2006 * SIA Roadmap, IEEE Spectrum, July 1999

11. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 111 Cost of Manufacturing Testing in 2000AD n 0.5-1.0GHz, analog instruments,1,024 digital pins: ATE purchase price = $1.2M + 1,024 x $3,000 = $4.272M n Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year n Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second

12. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 112 Roles of Testing n Detection: Determination whether or not the device under test (DUT) has some fault. n Diagnosis: Identification of a specific fault that is present on DUT. n Device characterization: Determination and correction of errors in design and/or test procedure. n Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.

13. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 113 A Modern VLSI Device System-on-a-chip (SOC) DSP cor e RAM ROM Inter- face logic Mixed- signal Codec Data terminal Transmission medium Figure 18.5 (page 605)

14. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 114 Course Outline Part I: Introduction n Basic concepts and definitions (Chapter 1) n Test process and ATE (Chapter 2) n Test economics and product quality (Chapter 3) n Fault modeling (Chapter 4)

15. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 115 Course Outline (Cont.) Part II: Test Methods n Logic and fault simulation (Chapter 5) n Testability measures (Chapter 6) n Combinational circuit ATPG (Chapter 7) n Sequential circuit ATPG (Chapter 8) n Memory test (Chapter 9) n Analog test (Chapters 10 and 11) n Delay test and IDDQ test (Chapters 12 and 13)

16. Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 116 Course Outline (Cont.) Part III: DFT n Scan design (Chapter 14) n BIST (Chapter 15) n Boundary scan and analog test bus (Chapters 16 and 17) n System test and core-based design (Chapter 18)