1. Properties of Real-World Digital Logic Diagrams Christine Alvarado, Harvey Mudd College Michael Lazzareschi, Pomona College May 24, 2007

2. Problem: Design a 1-bit full adder

3. CinBACoutSum 00000 00101 01001 01110 10001 10110 11010 11110 Correct! AND-2 XOR-2 OR-2

4. Disconnect between Sketching and Simulation "Most of the time the lab was more about battling Xilinx than actually learning anything useful" –HMC, E85 student

5. Bridging the Gap Between Sketching and Simulation Students should think about what they draw not how they draw it Few drawing restrictions + robust recognition requires understanding of natural drawing style

6. Seamless Integration? Goal: Recognize the sketches students already draw Problem: Sketch recognition is hard! noise in the sketch ambiguous shape boundaries

7. Drawing Style Restrictions One stroke/symbol (i.e., gesture-based input) Pause between symbols Symbols contain temporally contiguous strokes Are these restrictions natural?

8. Our study Data collection: Problem sets, notes labs from digital design class Drawn in Windows Journal (no recognition) Measured: Number of strokes per symbol Pause time between symbols Stroke order

9. Dataset 98 digital circuit diagrams extracted from 13 students' notes, problem sets and labs Stroke: time-ordered set of points (x, y, time) Diagram: time-ordered set of strokes

10. Dataset: Labeling A wireANDORNOTNANDNORXORlabel Digital Logic Symbols NAND label other wire

11. Results: Stroke Order Individual range: 70% - 96% AND NAND

12. Stroke Order: Qualitative Results Two patterns of non-consecutive strokes: Touch-up stroke Two-part gate drawing (particularly NAND gates)

13. Results: Stroke Timing

14. Stroke Timing: Best Threshold Error

15. Results: Strokes Per Symbol AND Gates Students use a range of drawing patterns Some students consistent, some inconsistent

16. Results: Strokes per Symbol AND vs. NOT AND NOT

17. Results: Strokes per Symbol wires Most wires drawn with 1 stroke… …yet some students > 5 strokes

18. Implications for Sketch Recognition Systems Pause time can aid stroke grouping Alone, it is not sufficient, but… …users might be willing to adapt their drawing style to increase pause time Recognition systems should not assume temporally contiguous strokes New recognition task: Identify touch-up strokes

19. Implications for Sketch Recognition Systems (2) Symbol recognizers must incorporate a wide range of drawing styles Stroke-based recognition schemes will be difficult User-specific learning is essential to recognition Pause time Consistency Number of strokes per symbol Stroke order

20. Future work Analyze additional domains Front End Circuit Recognition and Translation Simulation (Xilinx) Verilog file hand-drawn sketch Incorporate knowledge into recognition system design

21. Questions?