Download presentation
Presentation is loading. Please wait.
1
Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture Wei-Kai Cheng Youn-Long Lin* Computer & Communications Research Laboratories *CS Department, NTHU Taiwan
2
2 Overview u Features: –Auto-Increment/Decrement for Address Generation –Constraints for Loop Execution u Optimization Methods: –Multi-Phase Data Ordering –Graph-Based Address Register Allocation »Block Access Graph
3
3 Auto-Increment/Decrement
4
4 New Constraints u Loop Execution –Data Ordering Constraint –Address Register Allocation Constraint u Architectural Constraint –Different arrays are stored in disjoint memory space –Multiple auto-increment/decrement ranges in the instruction set architecture
5
5 Data Ordering Constraint
6
6 Address Register Allocation Constraint
7
7 Architectural Constraint
8
8 Data Lists
9
9 Approach u Split the access sequence into data lists –Array –Iteration Stride u Data Ordering u Address Register Allocation –Data Lists Merging or Splitting
10
10 Access Graph
11
11 Data Ordering
12
12 Address Register Allocation u # data lists > # address registers: –data list merging u # data lists < # address registers: –data list splitting
13
13 Two-Way Data List Splitting
14
14 Block Access Graph Construction
15
15 Block Access Graph Partition
16
16 Experimental Results * number of data lists and data ordering applied
17
17 Experimental Results (Cont.) * ratio over TI’s compiler in term of inserted instructions T: TI’s compiler O: Our algorithm o: data ordering a: address register allocation
18
18 Experimental Results (Cont.) * ratio over TI’s compiler in term of execution cycles T: TI’s compiler O: Our algorithm o: data ordering a: address register allocation
19
19 Conclusions u Data ordering is not so effective in loop execution u Data list splitting is more important than data list merging
Similar presentations
© 2025 SlidePlayer.com. Inc.
All rights reserved.