1. Digital Design: Chapters 1-5 1 Chapter 1. Introduction Digital Design - Logic Design? Analog versus Digital Once-analog now goes digital –Still pictures –Video recordings: Digital Versatile Disc (DVD) –Audio recordings –Automobile carburetors –Telephone system –Traffic lights –Movie effects

2. Digital Design: Chapters 1-5 2 Why favoring digital circuits over analog ones –Reproducibility –Ease of design –Flexibility and functionality –Programmability –Speed –Economy –Steadily advancing technology Digital devices –Gates: AND, OR, NOT, NAND, NOR, etc. –Flip-flops, latches Electronic Aspects of digital design –Noise margins (Fig. 1-2)

3. Digital Design: Chapters 1-5 3 Noise Margins DC noise margin –It is a measure of how much noise it takes to corrupt a worst case output voltage into a value that may not be recognized properly by an input (Fig. 3-26,Pages 100-102) –V OHmin : The minimum output voltage in the HIGH state –V IHmin : Then minimum input voltage guaranteed to be recognized as a HIGH –V ILmax : Then maximum input voltage guaranteed to be recognized as a LOW –V OLmax : Then maximum output voltage in the LOW state –Noise margin for HIGH state: V OHmax -V IHmin –Noise margin for LOW state: V ILmax -V OLmax

4. Digital Design: Chapters 1-5 4 Software Design Aspects of Digital Design –Synthesis –Analysis CAD tools support for design activities –Design descriptions Schematic entry Hardware Description Languages (HDLs): ABEL, VHDL, Verilog, etc. –Design Synthesis HDL compilers, Logic optimizer, Physical design synthesizer, etc. –Design Analysis Verification Simulation Timing analyzer Test benches

5. Digital Design: Chapters 1-5 5 Integrated Circuits (IC) –Wafer, die, chip –Small Scale Integration(SSI: 1 to 20 gates), Medium Scale Integration (MSI: 20 gates to 200 gates), Large Scale Integration (LSI: 200 gates 200000 gates), Very Large Scale Integration (VLSI: 200000 gates above) Programmable Logic Devices (PLD) –Programmable logic arrays (PLA): Two-level structure (AND- OR planes) –Programmable array logic (PAL) devices: Enhanced PLA –Complex PLD (CPLD): Multiple PLDs with programmable interconnection structure. –Field programmable gate array (FPGA): (Fig. 1-6) Application-Specific IC (ASIC) –Semi-custom ICs, chips are designed for a particular, limited product or applications Standard cells versus gate arrays Moore’s Law

6. Digital Design: Chapters 1-5 6 5.1.3 Signal Names and Active Levels Signal names Active levels –Active High A signal performs the named action or denotes the named condition when it is HIGH or 1. –Active Low A signal performs the named action or denotes the named condition when it is LOW or 0. –Asserted A signal is at its active level. –Deasserted or negated A signal is not at its active level. –Active-level naming convention (Table 5-1) –Active level for pins (Fig. 5-5, 5-6, 5-7, 5-8, 5-9, 5-10)

7. Digital Design: Chapters 1-5 7 Circuit Timing Transition time (Fig. 3-36) –The amount of time that the output of a logic circuit takes to change from one state to another Rise time: An output takes a certain time to change from LOW to HIGH Fall time: An output takes a certain time to change from High to LOW Propagation delay (Fig. 3-42) –A signal path is the electrical path from a particular input signal to a particular output signal of a logic element. –The propagation delay for a signal path is defined as the time that it takes a change t pHL : The time between an input change and the corresponding output change when the output is changing from HIGH to LOW

8. Digital Design: Chapters 1-5 8 t pLH : The time between an input change and the corresponding output change when the output is changing from LOW to HIGH –Minimum pulse width (Fig. 3-43) Timing diagram –It illustrates the logical behavior of signals in a digital circuit as a function of time. (Fig. 5-19) Timing specifications –Maximum, typical, minimum delays (Table 5-2, 5-3) Timing Analysis

9. Digital Design: Chapters 1-5 9 Power Consumption CMOS power consumption –Static power consumption (or dissipation) –Dynamic power consumption Short circuit power consumption Output load charged or discharged power consumption –Formulas:

10. Digital Design: Chapters 1-5 10 5.3 Combinational PLDs Programmable Logic Array (PLA) (Fig. 5-21, 5-22, 5- 23, 5-24) –Limitations The number of inputs, The number of outputs, and The number of product terms Programmable Array Logic (PAL) Devices (Fig. 5-25)