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Introduction to asynchronous circuit design: specification and synthesis Part II: Synthesis of control circuits from STGs.

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Presentation on theme: "Introduction to asynchronous circuit design: specification and synthesis Part II: Synthesis of control circuits from STGs."— Presentation transcript:

1 Introduction to asynchronous circuit design: specification and synthesis Part II: Synthesis of control circuits from STGs

2 Outline Overview of the synthesis flow Specification State graph and next-state functions State encoding Implementability conditions Speed-independent circuit –Complex gates –C-element architecture

3 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

4 x y z x+ x- y+ y- z+ z- Signal Transition Graph (STG) x y z

5 x y z x+ x- y+ y- z+ z-

6 x+ x- y+ y- z+ z- xyz 000 x+ 100 y+ z+ y+ 101 110 111 x- 001 011 y+ z- 010 y-

7 xyz 000 x+ 100 y+ z+ y+ 101 110 111 x- 001 011 y+ z- 010 y- Next-state functions

8 x z y

9 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

10 VME bus Device LDS LDTACK D DSr DSw DTACK VME Bus Controller Data Transceiver Bus DSr LDS LDTACK D DTACK Read Cycle

11 STG for the READ cycle LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDS LDTACK D DSr DTACK VME Bus Controller

12 Choice: Read and Write cycles DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK-DTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

13 Choice: Read and Write cycles DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

14 Choice: Read and Write cycles DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

15 Choice: Read and Write cycles DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

16 Circuit synthesis Goal: –Derive a hazard-free circuit under a given delay model and mode of operation

17 Speed independence Delay model –Unbounded gate / environment delays –Certain wire delays shorter than certain paths in the circuit Conditions for implementability: –Consistency –Complete State Coding –Persistency

18 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

19 STG for the READ cycle LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDS LDTACK D DSr DTACK VME Bus Controller

20 Binary encoding of signals DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS+

21 Binary encoding of signals DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS+ 10000 10010 10110 0111001110 01100 00110 10110 (DSr, DTACK, LDTACK, LDS, D)

22 QR (LDS+) QR (LDS-) Excitation / Quiescent Regions ER (LDS+) ER (LDS-) LDS- LDS+ LDS-

23 Next-state function 0  1 LDS- LDS+ LDS- 1  0 0  0 1  1 10110

24 Karnaugh map for LDS DTACK DSr D LDTACK 00011110 00 01 11 10 DTACK DSr D LDTACK 00011110 00 01 11 10 LDS = 0 LDS = 1 01-0 000000/1? 1 111 - - - --- ---- - ---- ---

25 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

26 Concurrency reduction LDS- LDS+ LDS- 10110 DSr+

27 Concurrency reduction LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+

28 State encoding conflicts LDS- LDTACK- LDTACK+ LDS+ 10110

29 Signal Insertion LDS- LDTACK- D- DSr- LDTACK+ LDS+ CSC- CSC+ 101101 101100

30 Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

31 Complex-gate implementation

32 Implementability conditions Consistency –Rising and falling transitions of each signal alternate in any trace Complete state coding (CSC) –Next-state functions correctly defined Persistency –No event can be disabled by another event (unless they are both inputs)

33 Implementability conditions Consistency + CSC + persistency There exists a speed-independent circuit that implements the behavior of the STG (under the assumption that ay Boolean function can be implemented with one complex gate)

34 Persistency 100000001 a- c+ b+b+ b+b+ a c b a c b is this a pulse ? Speed independence  glitch-free output behavior under any delay

35 a+ b+ c+ d+ a- b- d- a+ c-a- 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+

36 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ ab cd 00011110 00 01 11 10 1 11 11 1 0 0000 ER(d+) ER(d-)

37 ab cd 00011110 00 01 11 10 1 11 11 1 0 0000 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ Complex gate

38 Implementation with C elements C R S z  S+  z+  S-  R+  z-  R-  S (set) and R (reset) must be mutually exclusive S must cover ER(z+) and must not intersect ER(z-)  QR(z-) R must cover ER(z-) and must not intersect ER(z+)  QR(z+)

39 ab cd 00011110 00 01 11 10 1 11 11 1 0 0000 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d

40 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d but...

41 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d Assume that R=ac has an unbounded delay Starting from state 0000 (R=1 and S=0): a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ; R+ disabled (potential glitch)

42 ab cd 00011110 00 01 11 10 1 11 11 1 0 0000 0000 1000 1100 0100 0110 0111 1111 10111011 00111001 0001 a+ b+ c+ a- b- c- a+ c- a- d- d+ C S R d Monotonic covers

43 C-based implementations C S R d C d a b c a b c d weak a c d generalized C elements (gC) weak

44 Speed-independent implementations Implementability conditions –Consistency –Complete state coding –Persistency Circuit architectures –Complex (hazard-free) gates –C elements with monotonic covers –...

45 Synthesis exercise y- z-w- y+x+ z+ x- w+ 1011 0111 0011 1001 1000 1010 0001 00000101 00100100 0110 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ Derive circuits for signals x and z (complex gates and monotonic covers)

46 Synthesis exercise 1011 0111 0011 1001 1000 1010 0001 00000101 00100100 0110 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ wx yz 00011110 00 01 11 10 - - - - Signal x 1 0 1 1 1 1 1 0 0 0 0 0

47 Synthesis exercise 1011 0111 0011 1001 1000 1010 0001 00000101 00100100 0110 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ wx yz 00011110 00 01 11 10 - - - - Signal z 1 0 0 0 0 1 1 1 0 0 0 0

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