1. Huffman Encoder Project

2. Howd - Zur Hung Eric Lai Wei Jie Lee Yu - Chiang Lee Design Manager: Jonathan P. Lee Huffman Encoder Project Final Presentation April 30 th, 2007 Overall Project Objective: Design a Low Power Huffman Encoder

3. About Huffman Compression (Wei Jie) Marketing (Wei Jie) Project Description (Wei Jie) Design Methodology (Randal) Original Huffman Recipe (Randal) Our Huffman Encoder (Randal) Design Decisions (Randal) Behavioral/Algorithmic Description (Eric) Floorplan Evolution (Eric) Layout (John) Verification (Eric) Issues Encountered (John) Specifications (John) Conclusions (John) Agenda of Presentation

4. About Huffman Huffman is a compression algorithm Often used as a back-end to other compressions Greedy algorithm

5. The Need for Compression It is becoming a wireless world Wireless bandwidth limited Power is limited COMPRESSION! Reduce data size = Save power + time + bandwidth

6. Why Huffman? Lossless Statistical David Huffman is the man! Outdid Shannon-Fano coding

7. Project Description Our Huffman Encoder is a fast and power efficient solution to data compression with on-chip cache

8. Hardware compression out performs software based solution Small, affordable, and power efficient chip is perfect for portable devices Why Hardware?

9. Hardware Huffman Solution Low power, compact, full-custom ASIC Saves power, time, and system resources Compress data packets on network cards Cell phones, PDA, Laptop

10. Design Methodology 1.Understand the algorithm 2.Design functional blocks 3.Behavioral Verilog 4.Structural Verilog 5.Schematic 6.Layout 7.Simulations

11. Specifics of Huffman Procedure pre-scan data and count frequency iteratively find least two frequent word and build a tree encode word according to the final tree structure 472115 abcde 3 dc 7 a 14 b 29 e 0 0 0 0 1 1 1 1 00101000100001 abcde

12. Our Huffman Procedure pre-scan data, count frequency, and assign unique group number iteratively find least two frequent word to update group number and encoding finish encoding look up table 472115 abcde 01234 4733 abcde 01224 10 7777 abcde 01004 10100 14 15 abcde 00004 011001000 29 abcde 00000 001010000 1

13. 1.5-bit input word size 2.16-bit frequency 3.Two SRAMs 4.Adders: 16-bit Carry Select Adders 5.Serial output 6.Control logic to shut down modules Design Decisions

14. Behavioral / Algorithm Description turns off unused blocks to reduce power

15. Schematic Diagram

16. Floorplan Prelayout

17. Floorplan Midlayout

18. Final Chip Layout

19. Top Find2Freq Combine SRAM freqGroup SRAM codeLength countFreq serial output control

20. CountFrequency

21. Find2Freq

22. Combine

23. SerialOutput

24. SRAM (FreqGroup)

25. Poly

26. Metal 1

27. Metal 2

28. Metal 3

29. Metal 4

30. Matched Verilog results with MATLAB results Verified the successful compression of several test cases including parts of an image file: Verification: Verilog

31. Vigorously tested each block Combined them and encoded several words Verification: Schematic

32. Verified strong signal integrity Buffered high fan-outs and long wires Critical Path: 4.88 ns All outputs of modules go through registers Verification: Layout

33. Component Specifications countFreqfind2freqcombineSerial Output SRAM (combined) Transistor Count 71828102702140413764 Area (in μm 2 ) 265698449750438039041 Density 0.2700.2850.2770.3210.353 Power (mWatt) 0.4050.6150.6650.2419.19

34. Final Specifications Number of Transistors : 23,322 Area : 288.18 x 273.645 = 78859 μm 2 Density : 0.296 (transistors/μm2) Aspect Ratio = 1:1.05 Pin Count = 52 pins Input : 5-bit data input, start, done, finish Output : 36-bit treeOutput, treeReady, out, request, error vdd!, gnd!, clk, reset Final Clock Speed = 200 MHz

35. Final Specifications Final result is up to 1800 times faster than Java! (probably because it’s Java) Compressed 640 bits of an image Java results – 10 ms Centrino 1.5 GHz 512 RAM Our hardware Huffman – 5.4 us 1071 cycles

36. 1.Bad estimate for original floorplan 2.Long SRAM simulation time 3.SRAM sense amp issue 4.Too much poly! 5.Cannot route through SRAM Issues Encountered

37. Conclusions Next Steps: Scale up design Better compression ratio Higher throughput Meeting of the Minds HUFFMAN DECODER!!

38. Questions?