1. Digital Integrated Circuits© Prentice Hall 1995 Memory SEMICONDUCTOR MEMORIES

2. Digital Integrated Circuits© Prentice Hall 1995 Memory Chapter Overview

3. Digital Integrated Circuits© Prentice Hall 1995 Memory Semiconductor Memory Classification

4. Digital Integrated Circuits© Prentice Hall 1995 Memory Memory Architecture: Decoders

5. Digital Integrated Circuits© Prentice Hall 1995 Memory Array-Structured Memory Architecture

6. Digital Integrated Circuits© Prentice Hall 1995 Memory Hierarchical Memory Architecture

7. Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NOR ROM Layout

8. Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NOR ROM Layout

9. Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NAND ROM

10. Digital Integrated Circuits© Prentice Hall 1995 Memory MOS NAND ROM Layout

11. Digital Integrated Circuits© Prentice Hall 1995 Memory Precharged MOS NOR ROM

12. Digital Integrated Circuits© Prentice Hall 1995 Memory Characteristics of State-of-the-art NVM

13. Digital Integrated Circuits© Prentice Hall 1995 Memory Read-Write Memories (RAM)

14. Digital Integrated Circuits© Prentice Hall 1995 Memory 6-transistor CMOS SRAM Cell

15. Digital Integrated Circuits© Prentice Hall 1995 Memory CMOS SRAM Analysis (Write)

16. Digital Integrated Circuits© Prentice Hall 1995 Memory CMOS SRAM Analysis (Read)

17. Digital Integrated Circuits© Prentice Hall 1995 Memory 6T-SRAM — Layout V DD GND Q Q WL BL M1 M3 M4M2 M5M6

18. Digital Integrated Circuits© Prentice Hall 1995 Memory Resistance-load SRAM Cell

19. Digital Integrated Circuits© Prentice Hall 1995 Memory 3-Transistor DRAM Cell

20. Digital Integrated Circuits© Prentice Hall 1995 Memory 3T-DRAM — Layout BL2BL1GND RWL WWL M3 M2 M1

21. Digital Integrated Circuits© Prentice Hall 1995 Memory 1-Transistor DRAM Cell

22. Digital Integrated Circuits© Prentice Hall 1995 Memory DRAM Cell Observations

23. Digital Integrated Circuits© Prentice Hall 1995 Memory 1-T DRAM Cell

24. Digital Integrated Circuits© Prentice Hall 1995 Memory Periphery

25. Digital Integrated Circuits© Prentice Hall 1995 Memory Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

26. Digital Integrated Circuits© Prentice Hall 1995 Memory Dynamic Decoders

27. Digital Integrated Circuits© Prentice Hall 1995 Memory A NAND decoder using 2-input pre- decoders

28. Digital Integrated Circuits© Prentice Hall 1995 Memory 4 input pass-transistor based column decoder

29. Digital Integrated Circuits© Prentice Hall 1995 Memory 4-to-1 tree based column decoder

30. Digital Integrated Circuits© Prentice Hall 1995 Memory Sense Amplifiers

31. Digital Integrated Circuits© Prentice Hall 1995 Memory Differential Sensing - SRAM

32. Digital Integrated Circuits© Prentice Hall 1995 Memory Latch-Based Sense Amplifier

33. Digital Integrated Circuits© Prentice Hall 1995 Memory Open bitline architecture

34. Digital Integrated Circuits© Prentice Hall 1995 Memory DRAM Read Process with Dummy Cell

35. Digital Integrated Circuits© Prentice Hall 1995 Memory Programmable Logic Array

36. Digital Integrated Circuits© Prentice Hall 1995 Memory Pseudo-Static PLA

37. Digital Integrated Circuits© Prentice Hall 1995 Memory Dynamic PLA

38. Digital Integrated Circuits© Prentice Hall 1995 Memory Clock Signal Generation for self-timed dynamic PLA

39. Digital Integrated Circuits© Prentice Hall 1995 Memory PLA Layout

40. Digital Integrated Circuits© Prentice Hall 1995 Memory PLA versus ROM

41. Digital Integrated Circuits© Prentice Hall 1995 Memory Semiconductor Memory Trends Memory Size as a function of time: x 4 every three years

42. Digital Integrated Circuits© Prentice Hall 1995 Memory Semiconductor Memory Trends Increasing die size factor 1.5 per generation Combined with reducing cell size factor 2.6 per generation

43. Digital Integrated Circuits© Prentice Hall 1995 Memory Semiconductor Memory Trends Technology feature size for different SRAM generations